Abstract: A battery module includes at least one cell group, and a heat dissipating member coupled to one side of the at least one cell group to externally dissipate heat generated in the at least one cell group, wherein the at least one cell group includes at least one battery cell stack, a flame retardant cover coupled to the battery cell stack to encase both side surfaces and an upper portion of the battery cell stack, and a flame retardant member disposed between an upper surface of the battery cell stack and the flame retardant cover and formed of a porous material.

Abstract: A secondary battery includes a battery cell assembly in which a plurality of battery cells and one or more first insulating members are stacked; a second insulating member formed to cover at least a portion of one end of the battery cell assembly in a direction perpendicular to a stacking direction of the battery cells and the one or more first insulating members; an upper case located on the second insulating member; and a fire extinguishing member located between the second insulating member and the upper case.

Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

Abstract: A system-on-chip is provided. The SoC includes a system power supply circuit which outputs a first supply voltage, an intellectual property (IP) which receives the first supply voltage and operates at a second supply voltage, a supplemental power supply circuit which generates a supplemental voltage; and a comparator which compares the first supply voltage with the second supply voltage and outputs a comparison signal, wherein the supplemental voltage is provided to the IP based on the comparison signal.

Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: A semiconductor device and a semiconductor system are provided. A semiconductor device includes a monitoring circuit receiving a first operating voltage and a second operating voltage, which is different from the first operating voltage, from a Power Management Integrated Circuit (PMIC) and monitoring a duration of use of a System-on-Chip (SoC) at each of the first and second operating voltages; a processing circuit calculating a normalized value based on predetermined weight information from the duration of use of the SoC at each of the first and second operating voltages; and a voltage circuit determining whether to increase an operating voltage of the SoC by comparing the normalized value with a predetermined value.

Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

Abstract: A semiconductor device includes an inductor selectively connected to a power supply voltage and configured to store and release energy; a first transistor connected between the power supply voltage and the inductor and configured to provide the power supply voltage to the inductor; a second transistor connected to the first transistor in series, connected between the inductor and a ground voltage, and configured to provide the ground voltage to the inductor; a modulator configured to provide a modulation signal to a control circuit configured to control the first and second transistors by performing pulse width modulation (PWM); a current sensor configured to sense an amount of current passing through the first transistor and generate a first output signal based on the sensed amount of current; and a first overcurrent protection output generator configured to generate a second output signal based on the first output signal and a first reference signal.