Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.

Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.

Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.

Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.

Abstract: A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.

Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.

Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.

Abstract: A circuit for decoding a high speed Manchester encoded digital communication signal is provided. The circuit includes a pair of latch circuits which are used to detect clock edges in the encoded signal for providing respectively set and reset pulses to a third latch circuit, an output of which comprises the decoded data of the Manchester code signal. Additional logic is provided to extract a clock signal from the Manchester code signal.

Abstract: A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network is configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each successive transfer between neighboring nodes. The buffer locations are managed so that they can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.

Abstract: A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network may be configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each successive transfer between neighboring nodes. The buffer locations are managed so that a node can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.