Patents by Inventor Hokyun Ahn
Hokyun Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916140Abstract: Provided is a compound semiconductor device. The compound semiconductor device according to embodiments of the inventive concept includes a first semiconductor layer having a fin extending in a first direction on a substrate, an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer, a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode, a dielectric layer disposed between a top surface of the fin and the upper gate electrode, and a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate.Type: GrantFiled: October 22, 2021Date of Patent: February 27, 2024Assignee: Electronics and Telecommunications Research InstituteInventors: Sungjae Chang, Hokyun Ahn, Hyunwook Jung
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Publication number: 20220246751Abstract: Provided is a compound semiconductor device. The compound semiconductor device according to embodiments of the inventive concept includes a first semiconductor layer having a fin extending in a first direction on a substrate, an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer, a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode, a dielectric layer disposed between a top surface of the fin and the upper gate electrode, and a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate.Type: ApplicationFiled: October 22, 2021Publication date: August 4, 2022Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sungjae CHANG, Hokyun AHN, Hyunwook JUNG
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Patent number: 10608102Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.Type: GrantFiled: September 20, 2018Date of Patent: March 31, 2020Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Min Jeong Shin, Jeong Jin Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Hyung Sup Yoon, Hyung Seok Lee, Jong-Won Lim, Sungjae Chang, Hyunwook Jung, Kyu Jun Cho, Dong Min Kang, Dong-Young Kim, Seong-Il Kim, Sang-Heung Lee, Jongmin Lee, Hong Gu Ji
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Patent number: 10256811Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.Type: GrantFiled: July 20, 2017Date of Patent: April 9, 2019Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Woojin Chang, Jong-Won Lim, Dong Min Kang, Dong-Young Kim, Seong-il Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Min Jeong Shin, Hokyun Ahn, Hyung Sup Yoon, Sang-Heung Lee, Jongmin Lee, Sungjae Chang, Yoo Jin Jang, Hyunwook Jung, Kyu Jun Cho, Hong Gu Ji
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Publication number: 20190103483Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.Type: ApplicationFiled: September 20, 2018Publication date: April 4, 2019Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hokyun AHN, Min Jeong SHIN, Jeong Jin KIM, Hae Cheon KIM, Jae Won DO, Byoung-Gue MIN, Hyung Sup YOON, Hyung Seok LEE, Jong-Won LIM, Sungjae CHANG, Hyunwook JUNG, Kyu Jun CHO, Dong Min KANG, Dong-Young KIM, SEONG-IL KIM, Sang-Heung LEE, Jongmin LEE, Hong Gu JI
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Publication number: 20190081166Abstract: Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.Type: ApplicationFiled: July 6, 2018Publication date: March 14, 2019Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae Won DO, Dong Min KANG, Dong-Young KIM, SEONG-IL KIM, Hae Cheon KIM, Byoung-Gue MIN, Min Jeong SHIN, Hokyun AHN, Hyung Sup YOON, Sang-Heung LEE, Jongmin LEE, Jong-Won LIM, Sungjae CHANG, Yoo Jin JANG, Hyunwook JUNG, Kyu Jun CHO, Hong Gu JI
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Publication number: 20180145684Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.Type: ApplicationFiled: July 20, 2017Publication date: May 24, 2018Applicant: Electronics and Telecommunications Research InstituteInventors: Woojin CHANG, Jong-Won LIM, Dong Min KANG, Dong-Young KIM, Seong-il KIM, Hae Cheon KIM, Jae Won DO, BYOUNG-GUE MIN, Min Jeong SHIN, Hokyun AHN, Hyung Sup YOON, Sang-Heung LEE, JONGMIN LEE, Sungjae CHANG, Yoo Jin JANG, HYUNWOOK JUNG, Kyu Jun CHO, Hong Gu JI
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Patent number: 9634112Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a ?-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the ?-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.Type: GrantFiled: February 27, 2015Date of Patent: April 25, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup Yoon, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Seong-Il Kim, Sang Heung Lee, Dong Min Kang, Chull Won Ju, Jae Kyoung Mun
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Patent number: 9490214Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.Type: GrantFiled: September 4, 2015Date of Patent: November 8, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Byoung-Gue Min, Sang Choon Ko, Jong-Won Lim, Hokyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20150380354Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.Type: ApplicationFiled: September 4, 2015Publication date: December 31, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Byoung-Gue MIN, Sang Choon KO, Jong-Won LIM, Hokyun AHN, Hyung Sup YOON, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 9159612Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.Type: GrantFiled: September 9, 2013Date of Patent: October 13, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Byoung-Gue Min, Sang Choon Ko, Jong-Won Lim, Hokyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 9136396Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.Type: GrantFiled: May 30, 2013Date of Patent: September 15, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Choon Ko, Jae Kyoung Mun, Byoung-Gue Min, Young Rak Park, Hokyun Ahn, Jeong-Jin Kim, Eun Soo Nam
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Publication number: 20150171188Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a ?-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the ?-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.Type: ApplicationFiled: February 27, 2015Publication date: June 18, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup YOON, Byoung-Gue MIN, Jong-Won LIM, Hokyun AHN, Seong-Il Kim, Sang Heung LEE, Dong Min KANG, Chull Won JU, Jae Kyoung MUN
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Publication number: 20150129890Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.Type: ApplicationFiled: December 29, 2014Publication date: May 14, 2015Inventors: Hokyun AHN, Jong-Won LIM, Jeong-Jin KIM, Hae Cheon KIM, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 8952422Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.Type: GrantFiled: June 7, 2013Date of Patent: February 10, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Jong-Won Lim, Jeong-Jin Kim, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8941231Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.Type: GrantFiled: July 10, 2013Date of Patent: January 27, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Young Rak Park, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8901608Abstract: A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.Type: GrantFiled: June 3, 2013Date of Patent: December 2, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Jong-Won Lim, Hokyun Ahn, Woojin Chang, Dong Min Kang, Seong-Il Kim, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140167070Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.Type: ApplicationFiled: July 10, 2013Publication date: June 19, 2014Inventors: Young Rak PARK, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140166615Abstract: Mold structures for imprint lithography are provided. Mold chip patterns including patterns for nano structures are disposed on a mold substrate. A trench region is provided between the mold chip patterns. Protrusion portions protrude from a bottom surface of the trench region. The protrusion portions extend along the trench region in a plan view.Type: ApplicationFiled: July 11, 2013Publication date: June 19, 2014Inventors: Zin Sig KIM, Hokyun Ahn
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Publication number: 20140167111Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.Type: ApplicationFiled: June 7, 2013Publication date: June 19, 2014Inventors: Hokyun AHN, Jong-Won Lim, Jeong-Jin Kim, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam