Patents by Inventor Homayoun Talieh

Homayoun Talieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7282124
    Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: October 16, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Homayoun Talieh, Cyprian Uzoh, Bulent M. Basol
  • Patent number: 7257893
    Abstract: Consistent excess conductive material is provided for plated conductors in integrated circuit metallization, regardless of the size and depth of trenches/vias into which the conductive material is deposited. Accordingly, subsequent processing (e.g., material removal) can be consistent and efficient for wafers with different feature sizes (particularly different depths), and for wafers at different metallization levels.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: August 21, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Hung-Ming Wang, Bulent M. Basol, Homayoun Talieh
  • Patent number: 7250104
    Abstract: The methods and systems described provide for radiation assisted material deposition, removal, and planarization at a surface, edge, and/or bevel of a workpiece such as a semiconductor wafer. Exemplary processes performed on a workpiece surface having topographical features include radiation assisted electrochemical material deposition, which produces an adsorbate layer outside of the features to suppress deposition outside of the features and to encourage, through charge conservation, deposition into the features to achieve, for example, a planar surface profile. A further exemplary process is radiation assisted electrochemical removal of material, which produces an adsorbate layer in the features to suppress removal of material from the features and to encourage, through charge conservation, removal of material outside of the features so that, for example, a planar surface profile is achieved.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: July 31, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Cyprian E. Uzoh, Homayoun Talieh, Bulent M. Basol, Halit N. Yakupoglu
  • Patent number: 7247558
    Abstract: The invention provides a process for forming a planar copper structure on a wafer surface in a first module and a second module of a system. During the process, a copper layer is formed on the wafer surface by utilizing an electrochemical deposition process in the first module. After the deposition, the wafer is moved to the second module of the system and an electrochemical mechanical polishing process is applied to planarize the copper layer to a predetermined thickness. The first and second modules can be positioned in a cluster tool. The wafer is subsequently processed by selective copper CMP and selective barrier layer CMP, which are conducted in another cluster tool.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: July 24, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M Basol, Homayoun Talieh
  • Patent number: 7244347
    Abstract: Systems and methods to provide electrical contacts to a workpiece to facilitate electrotreating processes, including electroplating and electroetching processes are presented.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: July 17, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh, Cyprian E. Uzoh
  • Publication number: 20070128851
    Abstract: A system and a method of forming copper interconnect structures in a surface of a wafer is provided. The method includes a step of performing a planar electroplating process in an electrochemical mechanical deposition station for filling copper material into a plurality of cavities formed in the surface of the wafer. The electroplating continues until a planar layer of copper with a predetermined thickness is formed on the surface of the wafer. In a following chemical mechanical polishing step the planar layer is removed until the copper remains in the cavities, insulated from one another by exposed regions of the dielectric layer.
    Type: Application
    Filed: February 6, 2007
    Publication date: June 7, 2007
    Applicant: NOVELLUS SYSTEMS, INC.
    Inventors: Bulent Basol, Homayoun Talieh
  • Patent number: 7211186
    Abstract: Systems and methods to provide electrical contacts to a workpiece to facilitate electrotreating processes, including electroplating and electroetching processes are presented.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 7211174
    Abstract: Systems and methods to provide electrical contacts to a workpiece to facilitate electrotreating processes, including electroplating and electroetching processes are presented.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M Basol, Homayoun Talieh, Boguslaw A. Nagorski, Cyprian E. Uzoh, Jeffrey A. Bogart
  • Patent number: 7204743
    Abstract: A system for processing a conductive surface on a front surface of a wafer to form a metallic interconnect structure is disclosed. The system for processing comprises an electrochemical mechanical processing (ECMPR) module configured to form a substantially planarized conductive layer on the front surface of the wafer, a chamber within the ECMPR module configured to remove conductive material from an edge region of the wafer, a CMP module configured to receive the wafer from the ECMPR module and polish the planarized conductive layer on the surface of the wafer to form the metallic interconnect structure, and a robot configured to transfer the wafer from the ECMPR module to the chemical mechanical polish (CMP) module. In one aspect of the invention, the ECMPR module deposits conductive material on the front surface of the wafer. The ECMPR module removes at least a portion of the conductive layer from the front surface of the wafer.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: April 17, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 7204924
    Abstract: The present invention provides a method for forming a conductive film with uniform properties on a wafer surface that has features or cavities. During the process, the workpiece is rotated and laterally moved while an electrodeposition solution is delivered onto the wafer surface at a predetermined flow rate, and a potential difference is applied between the workpiece surface and the electrode. The workpiece is rotated about an axis at predetermined revolutions per minute so that an edge region of the workpiece has a first predetermined linear velocity due to the rotation. The workpiece has a second predetermined linear velocity due to the lateral motion. The second predetermined velocity may be larger than the first predetermined velocity. Further, the wafer may not be rotated.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: April 17, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 7198551
    Abstract: A chemical mechanical polishing apparatus includes a rotating plate on which a substrate received, and a polishing pad which moves across the substrate as it rotates on the plate to polish the substrate. The load of the pad against the substrate, and the rotary speed of the plate, may be varied to control the rate of material removed by the pad.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: April 3, 2007
    Assignee: Applied Materials, Inc.
    Inventor: Homayoun Talieh
  • Publication number: 20070066054
    Abstract: A method is provided for manufacturing removable contact structures on the surface of a substrate to conduct electricity from a contact member to the surface during electroprocessing. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact layer so that the contact member touches the contact layer as the electroprocessing is performed on the conductive layer.
    Type: Application
    Filed: September 21, 2005
    Publication date: March 22, 2007
    Inventors: Cyprian Uzoh, Bulent Basol, Hung-Ming Wang, Homayoun Talieh
  • Publication number: 20070050974
    Abstract: Consistent excess conductive material is provided for plated conductors in integrated circuit metallization, regardless of the size and depth of trenches/vias into which the conductive material is deposited. Accordingly, subsequent processing (e.g., material removal) can be consistent and efficient for wafers with different feature sizes (particularly different depths), and for wafers at different metallization levels.
    Type: Application
    Filed: June 5, 2006
    Publication date: March 8, 2007
    Inventors: Hung-Ming Wang, Bulent Basol, Homayoun Talieh
  • Patent number: 7172497
    Abstract: A system and a method of forming copper interconnect structures in a surface of a wafer is provided. The method includes a step of performing a planar electroplating process in an electrochemical mechanical deposition station for filling copper material into a plurality of cavities formed in the surface of the wafer. The electroplating continues until a planar layer of copper with a predetermined thickness is formed on the surface of the wafer. In a following chemical mechanical polishing step the planar layer is removed until the copper remains in the cavities, insulated from one another by exposed regions of the dielectric layer.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: February 6, 2007
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Publication number: 20070004316
    Abstract: An integrated process tool for chemical mechanical processing, cleaning and drying a semiconductor workpiece is provided. The integrated process tool includes a CMP module and a cleaning and drying module. After being processed, the workpiece is transported from the CMP module to the cleaning and drying module using a movable housing. In the cleaning and drying module, a cleaning mechanism is used to clean the workpiece while the workpiece is rotated and held by a support stucture of the movable housing. A drying mechanism of the cleaning and drying module picks up the workpiece from the moveable housing and spin dries it. Throughout the CMP process, cleaning and drying, the processed surface of the wafer faces down.
    Type: Application
    Filed: June 13, 2006
    Publication date: January 4, 2007
    Inventors: Jalal Ashjaee, Boris Govzman, Bernard Frey, Boguslaw Nagorski, Douglas Young, Bulent Basol, Homayoun Talieh
  • Patent number: 7147766
    Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: December 12, 2006
    Assignee: ASM NuTool, Inc.
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh, Bulent Basol
  • Patent number: 7129165
    Abstract: A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: October 31, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 7122473
    Abstract: The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof. The at least one nozzle is located in an upper chamber of a vertically configured processing subsystem that also includes mechanisms for plating, cleaning and drying in upper and lower chambers.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: October 17, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Jalal Ashjaee, Rimma Volodarsky, Cyprian E. Uzoh, Bulent M. Basol, Homayoun Talieh
  • Publication number: 20060219573
    Abstract: The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece.
    Type: Application
    Filed: June 1, 2006
    Publication date: October 5, 2006
    Inventors: Cyprian Uzoh, Homayoun Talieh, Bulent Basol, Douglas Young
  • Patent number: 7115510
    Abstract: The present invention relates to a process for forming a near-planar or planar layer of a conducting material, such as copper, on a surface of a workpiece using an ECMPR technique. The process preferably uses at least two separate plating solution chemistries to form a near-planar or planar copper layer on a semiconductor substrate that has features or cavities on its surface.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: October 3, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh, Cyprian E. Uzoh