Patents by Inventor Homayoun Talieh

Homayoun Talieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7097755
    Abstract: The present invention provides an apparatus for electrochemical mechanical processing of a surface of a workpiece by utilizing a process solution. The apparatus of the present invention includes an electrode touching the process solution, a belt workpiece surface influencing device extended between a supply spool and a receiving spool. During the process, the surface of the workpiece is placed in proximity of the workpiece surface influencing device and the process solution is flowed through the process section and onto the surface while a potential difference is applied between the electrode and the surface of the workpiece.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: August 29, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Halit N. Yakupoglu, Cyprian E. Uzoh, Homayoun Talieh
  • Patent number: 7097538
    Abstract: The methods and systems described provide for an in-situ endpoint detection for material removal processes such as chemical mechanical polishing (CMP) performed on a workpiece. In a preferred embodiment, an optical detection system is used to detect endpoint during the removal of planar conductive layers using CMP. An optically transparent polishing belt provides endpoint detection through any spot on the polishing belt. Once endpoint is detected, a signal can be used to terminate or alter a CMP process that has been previously initiated.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: August 29, 2006
    Assignee: ASM NuTool, Inc.
    Inventors: Homayoun Talieh, Bulent M. Basol
  • Publication number: 20060137994
    Abstract: A process of forming a conductive layer on a wafer is provided. A front surface and an edge surface of the wafer are coated with a seed layer. Further, the edge surface includes a back edge surface, a bevel surface and a front edge surface. During the process, the seed layer is removed from the back edge surface and the bevel surface using an etching process. Next, the conductive layer is formed by depositing a conductive material onto the remaining seed layer which coats the front edge surface and the front surface of the wafer. A part of the conductive layer which is on the front edge surface is then removed using another etching process.
    Type: Application
    Filed: February 18, 2004
    Publication date: June 29, 2006
    Inventors: Bulent Basol, Homayoun Talieh
  • Patent number: 7059944
    Abstract: An integrated process tool for chemical mechanical processing, cleaning and drying a semiconductor workpiece is provided. The integrated process tool includes a CMP module and a cleaning and drying module. After being processed, the workpiece is transported from the CMP module to the cleaning and drying module using a movable housing. In the cleaning and drying module, a cleaning mechanism is used to clean the workpiece while the workpiece is rotated and held by a support stucture of the movable housing. A drying mechanism of the cleaning and drying module picks up the workpiece from the moveable housing and spin dries it. Throughout the CMP process, cleaning and drying, the processed surface of the wafer faces down.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: June 13, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Jalal Ashjaee, Boris Govzman, Bernard M. Frey, Boguslaw A. Nagorski, Douglas W. Young, Bulent M. Basol, Homayoun Talieh
  • Publication number: 20060121725
    Abstract: The invention provides a process for forming a planar copper structure on a wafer surface in a first module and a second module of a system. During the process, a copper layer is formed on the wafer surface by utilizing an electrochemical deposition process in the first module. After the deposition, the wafer is moved to the second module of the system and an electrochemical mechanical polishing process is applied to planarize the copper layer to a predetermined thickness. The first and second modules can be positioned in a cluster tool. The wafer is subsequently processed by selective copper CMP and selective barrier layer CMP, which are conducted in another cluster tool.
    Type: Application
    Filed: March 23, 2005
    Publication date: June 8, 2006
    Inventors: Bulent Basol, Homayoun Talieh
  • Publication number: 20060118425
    Abstract: A layer structure usable in manufacturing an integrated circuit is made, in a single apparatus, by a particular process in which a patterned substrate is provided. An electrolyte solution, out of which a conductive material can be plated under an applied potential, is supplied over a surface of the patterned substrate, and a potential is applied so as to deposit a film of the conductive material out of the electrolyte solution and over the surface of the patterned substrate. The film of conductive material is preferably polished as it is deposited. The conductive material is then removed from field regions of the patterned substrate, while deposits of the conductive material are left in features defined in the patterned substrate. The deposits of the conductive material are then electrically isolated, resulting in the layer structure.
    Type: Application
    Filed: January 30, 2006
    Publication date: June 8, 2006
    Inventors: Bulent Basol, Cyprian Uzoh, Homayoun Talieh
  • Publication number: 20060070885
    Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
    Type: Application
    Filed: December 6, 2005
    Publication date: April 6, 2006
    Inventors: Cyprian Uzoh, Homayoun Talieh, Bulent Basol
  • Publication number: 20060063469
    Abstract: The methods and systems described provide for an in-situ endpoint detection for material removal processes such as chemical mechanical polishing (CMP) performed on a workpiece. In a preferred embodiment, an optical detection system is used to detect endpoint during the removal of planar conductive layers using CMP. An optically transparent polishing belt provides endpoint detection through any spot on the polishing belt. Once endpoint is detected, a signal can be used to terminate or alter a CMP process that has been previously initiated.
    Type: Application
    Filed: April 2, 2004
    Publication date: March 23, 2006
    Inventors: Homayoun Talieh, Bulent Basol
  • Publication number: 20060042934
    Abstract: The present invention is directed to a method and apparatus for plating a surface of a semiconductor workpiece (wafer, flat panel, magnetic films, etc.) using a liquid conductor that makes contact with the outer surface of the workpiece. The liquid conductor is stored in a reservoir and pump through an inlet channel to the liquid chamber. The liquid conductor is injected into a liquid chamber such that the liquid conductor makes contact with the outer surface of the workpiece. An inflatable tube is also provided to prevent the liquid conductor from reaching the back face of the workpiece. A plating solution can be applied to the front face of the workpiece where a retaining ring/seal further prevents the plating solution and the liquid conductor from making contact with each other. In an alternative embodiment, electrical contacts may be formed using an inflatable tube that has either been coated with a conductive material or contains a conductive object.
    Type: Application
    Filed: October 25, 2005
    Publication date: March 2, 2006
    Inventors: Homayoun Talieh, Bulent Basol
  • Publication number: 20060035569
    Abstract: An integrated system for processing a plurality of wafers, having a conductive front surface, is provided. The system includes a plurality of processing subsystems for depositing on or removing metal from the front surfaces of the wafers. Each processing subsystem includes a process chamber and a cleaning chamber. The system also has a wafer handling subsystem for transporting each of the wafers into or out of the appropriate one of the plurality of processing subsystems. The plurality of processing subsystems and wafer handling subsystem form an integrated system.
    Type: Application
    Filed: October 11, 2005
    Publication date: February 16, 2006
    Inventors: Jalal Ashjaee, Homayoun Talieh
  • Publication number: 20060030244
    Abstract: A chemical mechanical polishing apparatus includes a rotating plate on which a substrate received, and a polishing pad which moves across the substrate as it rotates on the plate to polish the substrate. The load of the pad against the substrate, and the rotary speed of the plate, may be varied to control the rate of material removed by the pad.
    Type: Application
    Filed: September 29, 2005
    Publication date: February 9, 2006
    Inventor: Homayoun Talieh
  • Patent number: 6988932
    Abstract: The present invention provides a wafer carrier that includes an opening, which in one embodiment is a plurality of holes, disposed along the periphery of the wafer carrier. A gas emitted through the holes onto a peripheral back edge of the wafer assists in preventing the processing liquids and contaminants resulting therefrom from reaching the inner region of the base and the backside inner region of the wafer. In another embodiment, a plurality of concentric sealing members are used to prove a better seal, and the outer seal is preferably independently movable to allow cleaning of a peripheral backside of the wafer to occur while the wafer is still attached to the wafer carrier.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: January 24, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Jalal Ashjaee, Homayoun Talieh, Bulent Basol, Konstantin Volodarsky
  • Publication number: 20060011485
    Abstract: The present invention relates to a method for forming a planar conductive surface on a wafer. In one aspect, the present invention uses a no-contact process with electrochemical deposition, followed by a contact process with electrochemical mechanical deposition.
    Type: Application
    Filed: September 20, 2005
    Publication date: January 19, 2006
    Inventors: Bulent Basol, Cyprian Uzoh, Homayoun Talieh
  • Publication number: 20060006073
    Abstract: A method and apparatus for electropolishing a conductive surface of a semiconductor wafer. The apparatus includes a polisher having at least one first electrode and at least one second electrode separated from one another by an isolation region.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 12, 2006
    Inventors: Bulent Basol, Homayoun Talieh
  • Publication number: 20060006060
    Abstract: An apparatus for processing a material on a surface of a wafer having a diameter includes a cavity defined by a peripheral wall terminating at a peripheral edge and having at least one lateral dimension smaller than the wafer diameter and at least one lateral dimension larger than the wafer diameter and configured to hold a process solution proximate to the peripheral edge such that the process solution will always contact a first wafer surface region, a head configured to hold the wafer above the cavity peripheral edge so that the surface of the wafer faces the cavity, and an electrical contact member positioned outside the cavity peripheral wall and configured to contact a second wafer surface region where the lateral dimension of the cavity is smaller than the wafer diameter and to maintain electrical contact with the wafer when the wafer is moved relative to the contact member. Advantages of the invention include substantially full surface treatment of the wafer.
    Type: Application
    Filed: September 13, 2005
    Publication date: January 12, 2006
    Inventors: Bulent Basol, Cyprian Uzoh, Homayoun Talieh
  • Patent number: 6974769
    Abstract: Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d1?0.5d2, with d1 being the first layer thickness and d2 being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d1?0.3d2.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: December 13, 2005
    Assignee: ASM NuTool, Inc.
    Inventors: Bulent Basol, Homayoun Talieh, Cyprian Uzoh
  • Publication number: 20050269212
    Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.
    Type: Application
    Filed: May 5, 2005
    Publication date: December 8, 2005
    Inventors: Homayoun Talieh, Cyprian Uzoh, Bulent Basol
  • Patent number: 6969456
    Abstract: The present invention relates to a containment chamber that is used for carrying out multiple processing steps such as depositing on, polishing, etching, modifying, rinsing, cleaning, and drying a surface on the workpiece. In one example of the present invention, the chamber is used to electro chemically mechanically deposit a conductive material on a semiconductor wafer. The same containment chamber can then be used to rinse and clean the same wafer. As a result, the present invention eliminates the need for separate processing stations for depositing the conductive material and cleaning the wafer. Thus, with the present invention, costs and physical space are reduced while providing an efficient apparatus and method for carrying out multiple processes on the wafer surface using a containment chamber.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: November 29, 2005
    Assignee: ASM Nutool, Inc.
    Inventors: Konstantin Volodarsky, Boguslaw A. Nagorski, Rimma Volodarsky, Douglas W. Young, Cyprian Uzoh, Homayoun Talieh
  • Patent number: 6958114
    Abstract: The present invention is directed to a method and apparatus for plating a surface of a semiconductor workpiece (wafer, flat panel, magnetic films, etc.) using a liquid conductor that makes contact with the outer surface of the workpiece. The liquid conductor is stored in a reservoir and pump through an inlet channel to the liquid chamber. The liquid conductor is injected into a liquid chamber such that the liquid conductor makes contact with the outer surface of the workpiece. An inflatable tube is also provided to prevent the liquid conductor from reaching the back face of the workpiece. A plating solution can be applied to the front face of the workpiece where a retaining ring/seal further prevents the plating solution and the liquid conductor from making contact with each other. In an alternative embodiment, electrical contacts may be formed using an inflatable tube that has either been coated with a conductive material or contains a conductive object.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: October 25, 2005
    Assignee: ASM Nutool, Inc.
    Inventors: Homayoun Talieh, Bulent Basol
  • Publication number: 20050227483
    Abstract: The present invention relates to a process for forming a near-planar or planar layer of a conducting material, such as copper, on a surface of a workpiece using an ECMPR technique. The process preferably uses at least two separate plating solution chemistries to form a near-planar or planar copper layer on a semiconductor substrate that has features or cavities on its surface.
    Type: Application
    Filed: November 22, 2004
    Publication date: October 13, 2005
    Inventors: Bulent Basol, Homayoun Talieh, Syprian Uzoh