Patents by Inventor Hong-Seng Shue
Hong-Seng Shue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120277Abstract: A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Hong-Seng SHUE, Sheng-Han TSAI, Kuo-Chin CHANG, Mirng-Ji LII, Kuo-Ching HSU
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Patent number: 11908790Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.Type: GrantFiled: January 6, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Li Yang, Po-Hao Tsai, Ching-Wen Hsiao, Hong-Seng Shue, Yu-Tse Su
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Patent number: 11854913Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.Type: GrantFiled: August 9, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Wei-Yu Chou, Hong-Seng Shue, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
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Patent number: 11855022Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.Type: GrantFiled: June 30, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11848270Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.Type: GrantFiled: May 25, 2019Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hong-Seng Shue, Sheng-Han Tsai, Kuo-Chin Chang, Mirng-Ji Lii, Kuo-Ching Hsu
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Publication number: 20230369255Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Inventors: Wei-Han CHIANG, Chun-Hung CHEN, Ching-Ho CHENG, Hong-Seng SHUE, Hsiao Ching-Wen, Ming-Da CHENG, Wei Sen CHANG
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Patent number: 11769741Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.Type: GrantFiled: May 27, 2022Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei-Han Chiang, Ming-Da Cheng, Ching-Ho Cheng, Wei Sen Chang, Hong-Seng Shue, Ching-Wen Hsiao, Chun-Hung Chen
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Publication number: 20230066360Abstract: A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.Type: ApplicationFiled: April 13, 2022Publication date: March 2, 2023Inventors: Kuan-Hung Chen, Hong-Seng Shue, Po-Hao Tsai, Mirng-Ji Lii
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Publication number: 20230065794Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Hong-Seng SHUE, Ming-Da CHENG, Ching-Wen HSIAO, Yao-Chun CHUANG, Yu-Tse SU, Chen-Shien CHEN
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Publication number: 20220367347Abstract: A chip structure is provided. The chip structure includes a substrate. The clip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Li YANG, Po-Hao TSAI, Ching-Wen HSIAO, Hong-Seng SHUE, Yu-Tse SU
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Publication number: 20220328440Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.Type: ApplicationFiled: June 30, 2022Publication date: October 13, 2022Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20220285295Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.Type: ApplicationFiled: May 27, 2022Publication date: September 8, 2022Inventors: Wei-Han CHIANG, Ming-Da CHENG, Ching-Ho CHENG, Wei Sen CHANG, Hong-Seng SHUE, Ching-Wen HSIAO, Chun-Hung CHEN
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Publication number: 20220246565Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.Type: ApplicationFiled: October 1, 2021Publication date: August 4, 2022Inventors: Ting-Li Yang, Po-Hao Tsai, Ching-Wen Hsiao, Hong-Seng Shue, Ming-Da Cheng
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Publication number: 20220216143Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.Type: ApplicationFiled: January 6, 2021Publication date: July 7, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Li YANG, Po-Hao TSAI, Ching-Wen HSIAO, Hong-Seng SHUE, Yu-Tse SU
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Patent number: 11380639Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.Type: GrantFiled: December 7, 2020Date of Patent: July 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11348884Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.Type: GrantFiled: November 13, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei-Han Chiang, Ming-Da Cheng, Ching-Ho Cheng, Wei Sen Chang, Hong-Seng Shue, Ching-Wen Hsiao, Chun-Hung Chen
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Patent number: 11342291Abstract: A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy pattern disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy pattern and the contact pad.Type: GrantFiled: May 6, 2020Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yao-Chun Chuang, Hong-Seng Shue, Chen-Nan Chiu, Li-Huan Chu, Mirng-Ji Lii
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Publication number: 20220157744Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventors: Wei-Han CHIANG, Ming-Da CHENG, Ching-Ho CHENG, Wei Sen CHANG, Hong-Seng SHUE, Ching-Wen HSIAO, Chun-Hung CHEN
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Publication number: 20210366794Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: YANG-CHE CHEN, WEI-YU CHOU, HONG-SENG SHUE, CHEN-HUA LIN, HUANG-WEN TSENG, VICTOR CHIANG LIANG, CHWEN-MING LIU
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Publication number: 20210351139Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii