Patents by Inventor Hong Sik Chae

Hong Sik Chae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079355
    Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.
    Type: Application
    Filed: November 1, 2023
    Publication date: March 7, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-su LEE, Hong Sik CHAE, Youn Soo KIM, Tae Kyun KIM, Youn Joung CHO
  • Publication number: 20240014252
    Abstract: A semiconductor device includes a substrate, first and second supporter patterns spaced vertically from the substrate, the second supporter pattern being spaced vertically from the first supporter pattern, a lower electrode hole extending vertically on the substrate, a lower electrode inside the lower electrode hole, contacting a sidewall of the first and second supporter patterns, the lower electrode including a first layer along a portion of a sidewall and bottom surface of the lower electrode hole, a second layer between the first layers, and a third layer on an upper surface of the first and second layers, the first and second layers including a material different from the second layer, and a sidewall of at least a portion of the third layer being concave toward the third layer, overlapping the second layer in the vertical direction, and being spaced apart from the second layer in the vertical direction.
    Type: Application
    Filed: March 10, 2023
    Publication date: January 11, 2024
    Inventors: Hong Sik CHAE, Tae Kyun KIM, Ji Hoon AN, Hyun-Suk LEE, Gi Hee CHO, Jae Hyoung CHOI
  • Patent number: 11848287
    Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: December 19, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-su Lee, Hong Sik Chae, Youn Soo Kim, Tae Kyun Kim, Youn Joung Cho
  • Patent number: 11812601
    Abstract: A semiconductor device includes a substrate, first and second supporter patterns stacked sequentially on the substrate in a first direction and spaced apart from an upper surface of the substrate, a lower electrode hole that extends through the first and second supporter patterns on the substrate in the first direction, an interface film on side walls and a bottom surface of the lower electrode hole, a lower electrode inside of the lower electrode hole on the interface film, a capacitor dielectric film that is in physical contact with side walls of the interface film, an uppermost surface of the interface film, and an uppermost surface of the lower electrode, the uppermost surface of the interface film is formed on a same plane as an upper surface of the second supporter pattern.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: November 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Goo Kang, Sang Hyuck Ahn, Sang Yeol Kang, Jin-Su Lee, Hyun-Suk Lee, Gi Hee Cho, Hong Sik Chae
  • Patent number: 11474093
    Abstract: The present invention relates to a method for screening protein-protein interaction inhibitors using a nanopore, a method for analyzing protein structures, a method for analyzing protein-protein interactions, and a kit therefor.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 18, 2022
    Assignees: Korea Research Institute of Bioscience and Biotechnology, Seoul National University R&DB Foundation
    Inventors: Seung Wook Chi, Ki Bum Kim, Dong Kyu Kwak, Mi Kyung Lee, Hong Sik Chae, Ji Hyang Ha
  • Publication number: 20220093532
    Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 24, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-su LEE, Hong Sik CHAE, Youn Soo KIM, Tae Kyun KIM, Youn Joung CHO
  • Publication number: 20220037325
    Abstract: A semiconductor device includes a substrate, first and second supporter patterns stacked sequentially on the substrate in a first direction and spaced apart from an upper surface of the substrate, a lower electrode hole that extends through the first and second supporter patterns on the substrate in the first direction, an interface film on side walls and a bottom surface of the lower electrode hole, a lower electrode inside of the lower electrode hole on the interface film, a capacitor dielectric film that is in physical contact with side walls of the interface film, an uppermost surface of the interface film, and an uppermost surface of the lower electrode, the uppermost surface of the interface film is formed on a same plane as an upper surface of the second supporter pattern.
    Type: Application
    Filed: April 1, 2021
    Publication date: February 3, 2022
    Inventors: Jun Goo Kang, Sang Hyuck Ahn, Sang Yeol Kang, Jin-Su Lee, Hyun-Suk Lee, Gi Hee Cho, Hong Sik Chae
  • Publication number: 20190162713
    Abstract: The present invention relates to a method for screening protein-protein interaction inhibitors using a nanopore, a method for analyzing protein structures, a method for analyzing protein-protein interactions, and a kit therefor.
    Type: Application
    Filed: July 24, 2018
    Publication date: May 30, 2019
    Applicants: Korea Research Institute of Bioscience and Biotech nology, Seoul National University R&DB Foundation
    Inventors: Seung Wook Chi, Ki Bum Kim, Dong Kyu Kwak, Mi Kyung Lee, Hong Sik Chae, Ji Hyang Ha