Abstract: A user equipment (UE) transmits concurrent channel state information (CSI) processing capability information to a base station. The capability information can take various forms, and is intended to constrain the base station in the types of CSI requests that can be made to the UE. For example, the UE may indicate different CSI processing capabilities for intra-CC and inter-CC cases and/or for different codebook types. The UE may also specify supported combinations of codebook types for concurrent CSI reporting. The UE may also specify maximum resources or weighting factors for different codebook types. The UE may further restrict the rank information it provides and use a priority rule for “dropping” CSI report data due to payload size restrictions. The base station may direct, or the UE may implement, improved utilization of CSI resources that are shared for multiple concurrent CSI reports. Minimum time requirements for CSI reporting may also be relaxed.

Abstract: Apparatuses, systems, and methods for multi-TRP by a UE, including out of order delivery of PDSCH, PUSCH, and/or DL ACK/NACK. The UE may receive, from a base station, a configuration that may include multiple control resource set (CORESET) pools and each CORESET pool may be associated with an index value. The UE may determine that at least two DCIs of the multiple DCIs end at a common symbol and determine, based on one or more predetermined rules, when the UE may be scheduled to receive PDSCHs, transmit PUSCHs, and/or transmit ACK/NACKs from CORESETs associated with the at least two DCIs.

Abstract: Apparatuses, systems, and methods for multi-TRP by a UE, including out of order delivery of PDSCH, PUSCH, and/or DL ACK/NACK. The UE may receive, from a base station, a configuration that may include multiple control resource set (CORESET) pools and each CORESET pool may be associated with an index value. The UE may determine that at least two DCIs of the multiple DCIs end at a common symbol and determine, based on one or more predetermined rules, when the UE may be scheduled to receive PDSCHs, transmit PUSCHs, and/or transmit ACK/NACKs from CORESETs associated with the at least two DCIs.

Abstract: The present invention provides methods for treating or ameliorating metabolic diseases, cholestatic liver diseases, or organ fibrosis, which comprises administering to a subject a therapeutically effective amount of a pharmaceutical composition comprising an isoxazole derivative, a racemate, an enantiomer, or a diastereoisomer thereof, or a pharmaceutically acceptable salt of the derivative, the racemate, the enantiomer, or the diastereoisomer.

Abstract: A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Abstract: Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Abstract: A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.

Abstract: An anti-fuse circuit includes an array of anti-fuses. Each anti-fuse has a tunneling magneto-resistance (TMR) element series connected with a transistor, such that breakdown of a magnetic tunnel junction (MTJ) in response to an applied first voltage stores fuse information. A sensing circuit senses and amplifies respective output signals provided by the anti-fuses.

Abstract: A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.

Abstract: A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.

Abstract: A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

Abstract: A memory system that includes a memory device and a memory controller. The memory device includes a plurality of memory cells, and a first storage unit configured to store information about a weak cell from among the plurality of memory cells. The memory controller is configured to transmit an operation command signal to the memory device, and control an operation of the memory device by using the information about the weak cell provided from the first storage unit. If the operation command signal is related to an operation to be performed using a first of the memory cells and the first memory cell is the weak cell, the memory device is configured to transmit the information about the weak cell to the memory controller.

Abstract: A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract: A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.