Abstract: A package structure, a packaging method and a semiconductor device are provided. The method includes: providing a semiconductor functional structure, an interconnecting layer disposed on a surface of the semiconductor functional structure; forming an isolation layer exposing part of the interconnecting layer, the exposed part of the interconnecting layer acting as a first pad, and the first pad used for performing a first type test; after completing the first type test, forming a redistribution layer on the first pad and the isolation layer, the redistribution layer and the interconnecting layer electrically connected; and forming a first insulating layer exposing parts of the redistribution layer, the exposed parts of the redistribution layer acting as a second pad and a third pad, the second pad used for performing a second type test, and the third pad used for executing a functional interaction corresponding to contents of the second type test.

Abstract: A DRAM memory includes: a substrate; a plurality of memory banks arranged in rows and columns on the substrate, each memory bank is divided into three memory blocks in the column direction. Each memory block has a number of memory cells arranged in rows and columns. Dividing each memory bank into three memory blocks in the column direction shortens the length of the memory bank in the row direction, as each memory bank has a certain capacity, so a large drive is no longer required. In addition, the distance from the control circuit and the data transmission circuit to the corresponding memory cell in the memory array in each memory bank will be shorter too, reducing parasitic resistance and parasitic capacitance generated from the data transmission circuit. As a result, the data transmission rate and data transmission accuracy are improved. The overall power consumption is reduced.

Abstract: Embodiments relate to a semiconductor memory and a method for writing data. The semiconductor memory includes: at least one storage array, the storage array including a plurality of data storage units and a plurality of check bit storage units; a check module, configured to receive written data and generate check data according to the written data; and a data transmission module, respectively connected to the check module and the storage array, the data transmission module being configured to transmit the written data to the plurality of data storage units and transmit the check data to the plurality of check bit storage units. A first transmission time duration of the check data is shorter than a second transmission time duration of the written data.

Abstract: The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.

Abstract: A DRAM memory includes: a substrate; a plurality of memory banks arranged in rows and columns on the substrate, each memory bank is divided into three memory blocks in the column direction. Each memory block has a number of memory cells arranged in rows and columns. Dividing each memory bank into three memory blocks in the column direction shortens the length of the memory bank in the row direction, as each memory bank has a certain capacity, so a large drive is no longer required. In addition, the distance from the control circuit and the data transmission circuit to the corresponding memory cell in the memory array in each memory bank will be shorter too, reducing parasitic resistance and parasitic capacitance generated from the data transmission circuit. As a result, the data transmission rate and data transmission accuracy are improved. The overall power consumption is reduced.

Abstract: A memory is provided. The memory includes banks, each bank includes a U half bank and a V half bank; a first error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of the output data of the U half banks and the V half banks.

Abstract: A semiconductor memory includes storage arrays, at least one verification module and gating circuits. Each verification module corresponds to multiple storage arrays. The verification module is configured to verify whether an error occurs in data information of the corresponding storage arrays. Each verification module is connected to a group of global data buses. The gating circuits are respectively connected to the storage arrays and the global data buses, and the gating circuits are configured to control on and off of a data transmission path connecting the global data buses to the storage arrays.

Abstract: Provided are a data transmission circuit and a memory. The data transmission circuit includes: a normal reading module, which is connected to a normal storage array and configured to read and output data from the normal storage array; a redundant reading module, which is connected to a redundant storage array, and configured to read and output data from the redundant storage array; and an error detection operation module, which is connected to the normal reading module and the redundant reading module respectively, and configured to synchronously receive the read data output from the normal reading module and the redundant reading module, and perform error detection operation on the read data.

Abstract: Disclosed is an integrated physiological signal detection sensor, comprising a movable housing member, a fixed housing member, and a sensing unit circuit board. The movable housing member and the fixed housing member are connected to form an internal space therebetween. The sensing unit circuit board is fixedly installed on the fixed housing member within the space. A piezoelectric film is attached to the sensing unit circuit board. A hollowed-out region surrounds the periphery of the piezoelectric film. A protrusion is provided on the movable housing member at a position corresponding to the piezoelectric film. The sensor of the present invention has advantages of simplified sensor installation, improved signal integrity, and simplified wire routing of an electromagnetic shield layer, thereby eliminating errors caused by sensor installation and improving the accuracy of data detection.

Abstract: A memory bank includes at least one storage module, each storage module including a read-write control circuit, a column decoding circuit and a plurality of storage arrays, the plurality of storage arrays being divided into a first unit and a second unit; a first decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the first unit; a second decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the second unit; a first data signal line; and a second data signal line.

Abstract: The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.

Abstract: Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.

Abstract: Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.

Abstract: Disclosed is a human body health assessment method and assessment system based on sleep big data. The method and the system acquire biometric data of a human body in a long-term, stable, and ever-increasing manner, and clearly and definitely describe the physical conditions of a human being and predict future health thereof using advanced data mining technology. The method comprises: acquiring, by a sensor mounted on a bed, various physiological data of a human body during sleep and storing the same to a cloud server; and obtaining a physiological evaluation index using an artificial intelligence learning model and generating a health status analysis report of the human body. By acquiring the data of the sensor mounted on the bed, data training of the artificial intelligence learning model is performed, to allow the model to automatically learn features related to the health of the human body.

Abstract: Disclosed is an integrated physiological signal detection sensor, comprising a movable housing member, a fixed housing member, and a sensing unit circuit board. The movable housing member and the fixed housing member are connected to form an internal space therebetween. The sensing unit circuit board is fixedly installed on the fixed housing member within the space. A piezoelectric film is attached to the sensing unit circuit board. A hollowed-out region surrounds the periphery of the piezoelectric film. A protrusion is provided on the movable housing member at a position corresponding to the piezoelectric film. The sensor of the present invention has advantages of simplified sensor installation, improved signal integrity, and simplified wire routing of an electromagnetic shield layer, thereby eliminating errors caused by sensor installation and improving the accuracy of data detection.

Abstract: Embodiments provide a test circuit and a memory chip. The test circuit is configured to read compressed data of a memory. The test circuit includes M storage blocks, wherein the M is an even number greater than or equal to 2. N storage blocks constitute one storage group, wherein the N is an even number greater than or equal to 2 and less than or equal to the M, and the M is an integral multiple of the N. The test circuit further includes a compressed data reading unit. One compressed data reading unit corresponds to one storage group. The compressed data reading unit is connected to the N storage blocks in the corresponding storage group. The compressed data reading unit receives a compressed data reading command and address information, and reads data in the N storage blocks according to the compressed data reading command and the address information.

Abstract: The application discloses a dental zirconia restoration material with uniform transition of strength and color, and a preparation method thereof. The preparation method includes the following steps: (1) pouring colored zirconia powder into a dry pressing mould in accordance with a sequence of the strength from high to low and the color from dark to light for each layer, and performing dry pressing; (2) performing isostatic cool pressing after the dry pressing; (3) performing pre-sintering after the isostatic cool pressing to obtain a greenware; and (4) performing CAD/CAM cutting on the greenware, and finally performing final sintering to obtain the dental zirconia restoration material. In the present application, the strength of a restoration can gradually increase from a cut end to the neck, the wear to adjacent teeth and jaw teeth is reduced, and long-bridge restoration can be realized due to the high strength of the neck.

Abstract: Disclosed are an anti-HER2 antibody and conjugate of the anti-HER2 antibody and small molecule medicine. Also disclosed are uses of the antibody and conjugate thereof in preparing medicine for treating tumor.

Abstract: Disclosed are an anti-HER2 antibody and conjugate of the anti-HER2 antibody and small molecule medicine. Also disclosed are uses of the antibody and conjugate thereof in preparing medicine for treating tumor.

Abstract: A traction drive elevator, comprising: an elevator car, a pair of guide rails, a counterweight, a traction drive motor comprising a housing, a stator, a rotor and a traction sheave; wherein the guide rails are disposed in a hoistway; both ends of the housing are symmetrically fixed to a side wall of the hoistway; the housing operates as a bearing beam; and the elevator car and the counterweight are suspended on the traction sheave of the traction drive motor via a plurality of wire ropes. Since the traction drive motor occupies no additional vertical space in the hoistway, space utilization ratio of the vertical space in the hoistway is increased, the height of the top floor is decreased, and building materials are saved.