Abstract: A touch-sensitive panel, touch-sensing method, and method for manufacturing the same are provided. The touch-sensitive panel includes a substrate, an induction line array layer, a dielectric layer, and an LED display panel. The induction line and the scanning line of the LED display panel intersect, and the induction line, the dielectric layer, and the scanning line form an inducing capacitor, which is utilized to generate a touch-sensing signal when the touch-sensitive panel is acted upon by an applied force. The present invention enables the display panel with the touch-sensing function to be thinner.

Abstract: The present invention provides a method for manufacturing a COA liquid crystal panel and a COA liquid crystal panel. The method includes forming a first pixel electrode layer on a color resist layer, forming a planarization layer on the first pixel electrode layer, and forming a second pixel electrode layer that is in engagement with the first pixel electrode layer on the planarization layer so as to achieve planarization of the pixel electrode layer to the maximum extent. Further, the second pixel electrode layer includes a pixel electrode block that is located in each sub pixel zone and has a lateral border located above a scan line and a longitudinal border located above a signal line so as to achieve self-shielding of light for the scan line and the signal line, allowing for omission of lateral and longitudinal black matrixes.

Abstract: The present invention provides a capacitive voltage dividing low color shift pixel circuit, which is electrically coupled to the main area (Main) of the sub pixel with a data signal line (Data) and provides a main data signal voltage thereto, and the data signal line (Data) is coupled to a common electrode line (Com) via a first capacitor (C1) and a second capacitor (C2) in series, and a routing (L) is led out between the first capacitor (C1) and the second capacitor (C2), and is electrically coupled to the sub area (Sub) and provides a sub data signal voltage thereto; with voltage dividing function of the first capacitor (C1) and the second capacitor (C2), the sub data signal voltage is different from the main data signal voltage. It can be realized to input different data signal voltages to the main area (Main) and the sub area (Sub) of the sub pixel with one data signal line (Data) to perform multi-domain display.

Abstract: An array substrate and a manufacturing method for the same are disclosed. The manufacturing method includes a step of forming a top-gate type thin-film transistor including steps of forming a source electrode and a drain electrode on a substrate; sequentially and stackedly forming an organic semiconductor layer, a first insulation layer and a gate electrode on the source electrode and the drain electrode; and using the gate electrode as a hard mask, and utilizing an etching technology for patterning the first insulation layer and the organic semiconductor layer one by one. The top-gate type thin-film transistor which is manufactured by the above method and using the gate electrode as a hard mask for sequentially patterning the first insulation layer and the organic semiconductor layer is simple in the manufacturing process, and can prevent the organic semiconductor layer from damaging.

Abstract: Disclosed are a field effect transistor and method for manufacturing the same, and a display device. The field effect transistor includes: a source and a drain which are spaced apart from each other; a semi-conductor layer arranged between the source and the drain; a first gate layer located on a side of the semi-conductor layer; and a second gate layer located on the other side of the semi-conductor layer. The field effect transistor provided by the present disclosure is less energy-consuming; a method for manufacturing the same is low costing; and a display device using the same is also less energy-consuming.

Abstract: The embodiment of the disclosure discloses a method of manufacturing the dual gate device, comprising: forming a first metal layer on a substrate; patterning the first metal layer through a first mask to form a bottom gate electrode; coating a first organic isolation layer on the bottom gate electrode and the substrate; sputtering a second metal layer on the first organic isolation layer; patterning the second metal layer to form a source-drain electrode; disposing an organic semiconductor layer, a second organic isolation layer and a third metal layer sequentially on the source-drain electrode and the first organic isolation layer; and patterning the organic semiconductor layer, the second organic isolation layer and the third metal layer through a third mask to form a top gate electrode. The top gate electrode overlapping the source-drain electrode makes the dual gate device to reduce the device contact resistance and saves the power consumption.

Abstract: The present invention provides a method for manufacturing a COA liquid crystal panel and a COA liquid crystal panel. The method includes forming a first pixel electrode layer on a color resist layer, forming a planarization layer on the first pixel electrode layer, and forming a second pixel electrode layer that is in engagement with the first pixel electrode layer on the planarization layer so as to achieve planarization of the pixel electrode layer to the maximum extent. Further, the second pixel electrode layer includes a pixel electrode block that is located in each sub pixel zone and has a lateral border located above a scan line and a longitudinal border located above a signal line so as to achieve self-shielding of light for the scan line and the signal line, allowing for omission of lateral and longitudinal black matrixes.

Abstract: The present disclosure relates to a pixel cell circuit of compensation feedback voltage. The pixel cell circuit is provided with the compensation capacitance (C_co), one end of the compensation capacitance (C_co) electrically connects to the compensation level wirings G(m)_co, and the other end of the compensation capacitance (C_co) electrically connects to the drain of the TFT (T1) and the pixel electrode (P). A level of the compensation signals transmitted by the compensation level wirings G(m)_co is opposite to the level of the scanning signals transmitted by the scanning lines G(m). When the pixel electrode has been fully charged, the compensation capacitance generates a pull-up feedback voltage for compensating the pull-down voltage caused by the parasitic capacitance so as to eliminate the effects toward the pixel electrodes caused by the scanning signals transmitted by the scanning lines. This configuration not only decreases the flickers, but also the image sticking.

Abstract: The present invention provides a capacitive voltage dividing low color shift pixel circuit, which is electrically coupled to the main area (Main) of the sub pixel with a data signal line (Data) and provides a main data signal voltage thereto, and the data signal line (Data) is coupled to a common electrode line (Com) via a first capacitor (C1) and a second capacitor (C2) in series, and a routing (L) is led out between the first capacitor (C1) and the second capacitor (C2), and is electrically coupled to the sub area (Sub) and provides a sub data signal voltage thereto; with voltage dividing function of the first capacitor (C1) and the second capacitor (C2), the sub data signal voltage is different from the main data signal voltage. It can be realized to input different data signal voltages to the main area (Main) and the sub area (Sub) of the sub pixel with one data signal line (Data) to perform multi-domain display.

Abstract: The present invention provides a method for manufacturing a COA liquid crystal panel and a COA liquid crystal panel. The method includes forming a planarization layer on a color resist layer to eliminate height difference resulting from stacking or overlapping of adjacent color resist blocks and also includes forming a pixel electrode layer on the planarization layer to set a pixel electrode block thereof located above sub pixel zones in such a way that a lateral border thereof is located above a scan line and a longitudinal border thereof is located above a signal line, whereby the array substrate achieves self-shielding of leaking light in the lateral direction by means of the scan line and also achieve self-shielding of leaking light in the longitudinal direction by means of the signal line and thus no black matrix is necessary is shielding leaking light.

Abstract: The present invention discloses an organic thin film transistor array substrate and a fabrication method thereof. The fabrication method is that a metal layer is first deposited successively on a substrate and followed by depositing a layer of Indium Tin Oxide (ITO), and then a photoresist layer is covered thereon to form a data line, a source electrode, a drain electrode and a pixel electrode by a first mask process. Subsequently, an organic semiconductor layer, a gate electrode, a scanning line, and a passivation layer are formed successively. Finally, a region where the pixel electrode, i.e. an anode of an OLED device, is situated and covered with the passivation layer is excavated an opening and allowing the underlying pixel electrode to be exposed to the outside. Then, a layer of OLED material is deposited on the exposed ITO pixel electrode to form an OLED device.

Abstract: The present invention provides a high quality liquid crystal display pixel circuit, and a plurality of sub pixels arranged in array, and each sub pixel is divided into a main area (Main) and a sub area (Sub), and one data signal line, a voltage dividing unit (10) and a routing are provided in accordance with sub pixels of each column; a Nth data line (D(N)) is electrically coupled to the main areas (Main) of the sub pixels of Nth column and provides a main data signal voltage to the same, and the corresponding Nth routing (L(N)) is led out from the voltage dividing unit (10), and is electrically coupled to the sub areas (Sub) of the sub pixels of the next column, N+1 column and provides a sub data signal voltage acquired by performing voltage dividing to the main data signal voltage with the voltage dividing unit (10) to the same; polarities of the main data signal voltage provided by the Nth data signal line (D(N)) and the main data signal voltage provided by the next N+1th data signal line (D(N+1)) are oppo

Abstract: The present disclosure relates to a pixel cell circuit of compensation feedback voltage. The pixel cell circuit is provided with the compensation capacitance (C_co), one end of the compensation capacitance (C_co) electrically connects to the compensation level wirings G(m)_co, and the other end of the compensation capacitance (C_co) electrically connects to the drain of the TFT (T1) and the pixel electrode (P). A level of the compensation signals transmitted by the compensation level wirings G(m)_co is opposite to the level of the scanning signals transmitted by the scanning lines G(m). When the pixel electrode has been fully charged, the compensation capacitance generates a pull-up feedback voltage for compensating the pull-down voltage caused by the parasitic capacitance so as to eliminate the effects toward the pixel electrodes caused by the scanning signals transmitted by the scanning lines. This configuration not only decreases the flickers, but also the image sticking.

Abstract: The present invention provides a high quality liquid crystal display pixel circuit, and a plurality of sub pixels arranged in array, and each sub pixel is divided into a main area (Main) and a sub area (Sub), and one data signal line, a voltage dividing unit (10) and a routing are provided in accordance with sub pixels of each column; a Nth data line (D(N)) is electrically coupled to the main areas (Main) of the sub pixels of Nth column and provides a main data signal voltage to the same, and the corresponding Nth routing (L(N)) is led out from the voltage dividing unit (10), and is electrically coupled to the sub areas (Sub) of the sub pixels of the next column, N?1 column and provides a sub data signal voltage acquired by performing voltage dividing to the main data signal voltage with the voltage dividing unit (10) to the same; polarities of the main data signal voltage provided by the Nth data signal line (D(N)) and the main data signal voltage provided by the next N+1th data signal line (D(N+1)) are oppo

Abstract: A liquid crystal display panel is disclosed and has data lines, scanning lines and pixel units. Each pixel units includes a first sub-pixel unit and a second sub-pixel unit. A top electrode of a first storage capacitor of the first sub-pixel unit is connected to a common electrode; a bottom electrode plate of the first storage capacitor is connected to a pixel electrode of the corresponding pixel unit. A top electrode of a second storage capacitor of the second sub-pixel unit is connected to a pixel electrode of the corresponding pixel unit; and a bottom electrode plate of the second storage capacitor is connected to the common electrode.

Abstract: The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.

Abstract: A liquid crystal display panel and a manufacturing method thereof are provided. The liquid crystal display panel includes a color resist layer, a planarization layer, and a pixel electrode layer. The color resist layer includes a first color resist unit and a second color resist unit, both of which are respectively disposed in two adjacent pixel units. The first color resist unit and the second color resist unit herein form a common boundary above the data line. The planarization layer is disposed on the color resist layer and utilized to planarize the common boundary. The pixel electrode layer which is disposed on the planarization layer includes a plurality of pixel electrode patterns corresponding to the pixel units, and borderlines of two adjacent pixel electrode patterns are located above the data line. The liquid crystal display panel of the present invention omits a black matrix for enhancing aperture ratio.

Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.

Abstract: The present application relates to a sub-pixel structure, a liquid crystal display device and a method for reducing color shift, the sub-pixel structure comprises a main area, a sub area and a signal wire, and the sub-pixel structure further comprises a first voltage dividing unit, the signal wire is connected to the main area and is connected to the sub area via the voltage dividing unit; the signal wire respectively provides different driving voltages for the main area and the sub area for reducing color shift in a liquid crystal display device. The present application has advantages on solving the color shift in relation to viewing angle in LCDs and greatly reducing cost.