Patents by Inventor Howard E. Rhodes

Howard E. Rhodes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150349004
    Abstract: An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 3, 2015
    Inventors: Yin Qian, Hsin-Chih Tai, Tiejun Dai, Duli Mao, Cunyu Yang, Howard E. Rhodes
  • Patent number: 9177982
    Abstract: A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: November 3, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Dyson H. Tai, Vincent Venezia, Yin Qian, Gang Chen, Howard E. Rhodes
  • Patent number: 9147776
    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the first polarity charge layer.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: September 29, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Dajiang Yang, Gang Chen, Duli Mao, Vincent Venezia
  • Patent number: 9142581
    Abstract: An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: September 22, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Hsin-Chih Tai, Tiejun Dai, Duli Mao, Cunyu Yang, Howard E. Rhodes
  • Publication number: 20150236058
    Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is coupled to selectively transfer the image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure disposed in the semiconductor material. The DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. The DTI structure includes a doped semiconductor material disposed inside the DTI structure that is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Inventors: Sing-Chung Hu, Rongsheng Yang, Gang Chen, Howard E. Rhodes, Sohei Manabe, Dyson H. Tai
  • Patent number: 9105767
    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. The first polarity charge layer is disposed between a first one of a plurality of passivation layers and a second one of the plurality of passivation layers disposed over the photodiode region.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: August 11, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Dajiang Yang, Gang Chen, Duli Mao, Vincent Venezia
  • Patent number: 9083899
    Abstract: Techniques and mechanisms for a pixel array to provide a level of conversion gain. In an embodiment, the pixel array includes conversion gain control circuitry to be selectively configured at different times for different operational modes, each mode for implementing a respective conversion gain. The conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—a supply voltage. In another embodiment, the conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—sample and hold circuitry.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: July 14, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Vincent Venezia, Gang Chen, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 9054007
    Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: June 9, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Sing-Chung Hu, Rongsheng Yang, Gang Chen, Howard E. Rhodes, Sohei Manabe, Hsin-Chih Tai
  • Patent number: 9042697
    Abstract: A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower cladding. Since upper surfaces of the resonator and waveguide are substantially coplanar, the aspect ratio, as between the waveguide and resonator in an area where the waveguide and resonator front one another, decreases thereby increasing the bandwidth of the resonator. The depression is formed by photomasking and etching the lower cladding before forming the resonator and waveguide. Pluralities of resonators are also taught that are formed in a plurality of depressions of the lower cladding. To decrease resonator bandwidth, waveguide(s) are formed in the depression(s) of the lower cladding while the resonator is formed on the surface. Thermo optic devices formed with these resonators are also taught.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Guy T. Blalock, Howard E. Rhodes
  • Publication number: 20150130080
    Abstract: A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventor: Howard E. Rhodes
  • Publication number: 20150091119
    Abstract: Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 10, 2014
    Publication date: April 2, 2015
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Publication number: 20150054106
    Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Inventors: Gang Chen, Ashish Shah, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Publication number: 20150048427
    Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: Omnivision Technologies, Inc.
    Inventors: Sing-Chung Hu, Rongsheng Yang, Gang Chen, Howard E. Rhodes, Sohei Manabe, Hsin-Chih Tai
  • Patent number: 8957359
    Abstract: Embodiments of the invention describe providing a compact solution to provide high dynamic range imaging (HDRI or simply HDR) for an imaging pixel by utilizing a control node for resetting a floating diffusion node to a reference voltage value and for selectively transferring an image charge from a photosensitive element to a readout node. Embodiments of the invention further describe control node to have to a plurality of different capacitance regions to selectively increase the overall capacitance of the floating diffusion node. This variable capacitance of the floating diffusion node increases the dynamic range of the imaging pixel, thereby providing HDR for the host imaging system, as well as increasing the signal-to-noise ratio (SNR) of the imaging system.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: February 17, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 8951910
    Abstract: A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 8952309
    Abstract: Techniques and architectures for providing a coating for one or more micro-lenses of a pixel array. In an embodiment, a pixel element includes a micro-lens and a coating portion extending over a surface of the micro-lens, where a profile of the coating portion is super-conformal to, or at least conformal to, a profile of the micro-lens. In another embodiment, the coating portion is formed at least in part by orienting the surface of the micro-lens to face generally downward with the direction of gravity, the orienting to allow a fluid coating material to flow for formation of the coating portion.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: February 10, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Hsin-Chih Tai, Duli Mao, Howard E. Rhodes
  • Patent number: 8946795
    Abstract: Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: February 3, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Sing-Chung Hu, Duli Mao, Hsin-Chih Tai, Yin Qian, Vincent Venezia, Rongsheng Yang, Howard E. Rhodes
  • Patent number: 8941159
    Abstract: Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: January 27, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 8933544
    Abstract: An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: January 13, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Yin Qian, Tiejun Dai, Howard E. Rhodes, Hongli Yang
  • Patent number: RE45357
    Abstract: A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and readout logic is formed in a second p-well. The first p-well can be selectively doped to optimize cross-talk, collection efficiency and transistor leakage, thereby improving the quantum efficiency of the sensor array while the second p-well can be selectively doped and/or biased to improve the speed and drive of the readout circuitry.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: February 3, 2015
    Assignee: Round Rock Research, LLC
    Inventor: Howard E. Rhodes