Patents by Inventor Howard E. Rhodes

Howard E. Rhodes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8658956
    Abstract: An image sensor provides high scalability and reduced image lag. The sensor includes a first imaging pixel that has a first photodiode region formed in a substrate of the image sensor. The sensor also includes a first vertical transfer transistor coupled to the first photodiode region. The first vertical transfer transistor can be used to establish an active channel. The active channel typically extends along the length of the first vertical transfer transistor and couples the first photodiode region to a floating diffusion.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: February 25, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Vincent Venezia, Hsin-Chih Tai, Duli Mao, Howard E. Rhodes
  • Publication number: 20140048897
    Abstract: Embodiments of a pixel including a substrate having a front surface and a photosensitive region formed in or near the front surface of the substrate. An isolation trench is formed in the front surface of the substrate adjacent to the photosensitive region. The isolation trench includes a trench having a bottom and sidewalls, a passivation layer formed on the bottom and the sidewalls, and a filler to fill the portion of the trench not filled by the passivation layer.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 20, 2014
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Yin Qian, Hsin-Chih Tai, Gang Chen, Duli Mao, Vincent Venezia, Howard E. Rhodes
  • Publication number: 20140035089
    Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.
    Type: Application
    Filed: October 14, 2013
    Publication date: February 6, 2014
    Applicant: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Dyson H. Tai, Keh-Chiang Ku, Vincent Venezia, Duli Mao, Wei Zheng, Howard E. Rhodes
  • Patent number: 8643132
    Abstract: Embodiments of the invention describe providing high dynamic range imaging (HDRI or simply HDR) to an imaging pixel by coupling a floating diffusion node of the imaging pixel to a plurality of metal-oxide semiconductor (MOS) capacitance regions. It is understood that a MOS capacitance region only turns “on” (i.e., changes the overall capacitance of the floating diffusion node) when the voltage at the floating diffusion node (or a voltage difference between a gate node and the floating diffusion node) is greater than its threshold voltage; before the MOS capacitance region is “on” it does not contribute to the overall capacitance or conversion gain of the floating diffusion node. Each of the MOS capacitance regions will have different threshold voltages, thereby turning “on” at different illumination conditions. This increases the dynamic range of the imaging pixel, thereby providing HDR for the host imaging system.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: February 4, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Publication number: 20140014813
    Abstract: An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Duli Mao, Hsin-Chih Tai, Yin Qian, Tiejun Dai, Howard E. Rhodes, Hongli Yang
  • Patent number: 8575035
    Abstract: A method of forming trenches in a semiconductor device includes forming an etchant barrier layer above a first portion of a semiconductor layer. A first trench is etched in a second portion of the semiconductor layer using a first etchant. The second portion of the semiconductor layer is not disposed underneath the etchant barrier layer. The etchant barrier layer is etched through using a second etchant that does not substantially etch the semiconductor layer. A second trench is etched in the first portion of the semiconductor layer using a third etchant. The third etchant also extends a depth of the first trench.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: November 5, 2013
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Publication number: 20130285183
    Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.
    Type: Application
    Filed: June 26, 2013
    Publication date: October 31, 2013
    Inventors: Gang Chen, Ashish Shah, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 8569856
    Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: October 29, 2013
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Hsin-Chih Tai, Keh-Chiang Ku, Vincent Venezia, Duli Mao, Wei Zheng, Howard E. Rhodes
  • Publication number: 20130277721
    Abstract: A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.
    Type: Application
    Filed: June 11, 2013
    Publication date: October 24, 2013
    Inventor: Howard E. Rhodes
  • Publication number: 20130264688
    Abstract: An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 10, 2013
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Yin Qian, Hsin-Chih Tai, Duli Mao, Tiejun Dai, Howard E. Rhodes, Hongli Yang
  • Publication number: 20130258144
    Abstract: Embodiments of the invention describe a system, apparatus and method for obtaining black reference pixels for dark current correction processing are described herein. Embodiments of the invention capture image signal data via a plurality of pixel cells of a pixel unit of an image device, wherein capturing image signal data involves establishing a first state of exposing incident light on each pixel of the pixel unit and a second state of shielding incident light from one or more pixels of the pixel unit via a shutter unit disposed over the pixel unit. Image signal data from each pixel of the pixel unit captured during the first state and the second state is read, and scene image data is created by combining a subset of image signal data captured during the first state with a dark current component including a subset of image signal data captured during the second state.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Publication number: 20130256509
    Abstract: Techniques for providing a pixel cell which includes two source follower transistors. In an embodiment, a first source follower transistor of a pixel cell and a second source follower transistor of the pixel cell are coupled in parallel with one another, where the source follower transistors are each coupled via their respective gates to a floating diffusion node of the pixel cell. In another embodiment, the first source follower transistor and second source follower transistor each operate based on a voltage of the floating diffusion node to provide a respective component of an amplification signal, where the pixel cell outputs an analog signal based on the amplification signal.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Cunyu Yang, Howard E. Rhodes
  • Publication number: 20130217173
    Abstract: A method of forming trenches in a semiconductor device includes forming an etchant barrier layer above a first portion of a semiconductor layer. A first trench is etched in a second portion of the semiconductor layer using a first etchant. The second portion of the semiconductor layer is not disposed underneath the etchant barrier layer. The etchant barrier layer is etched through using a second etchant that does not substantially etch the semiconductor layer. A second trench is etched in the first portion of the semiconductor layer using a third etchant. The third etchant also extends a depth of the first trench.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 22, 2013
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 8513762
    Abstract: A backside illuminated imaging sensor includes a vertical stacked sensor that reduces cross talk by using different silicon layers to form photodiodes at separate levels within a stack (or separate stacks) to detect different colors. Blue light-, green light-, and red light-detection silicon layers are formed, with the blue light detection layer positioned closest to the backside of the sensor and the red light detection layer positioned farthest from the backside of the sensor. An anti-reflective coating (ARC) layer can be inserted in between the red and green light detection layers to reduce the optical cross talk captured by the red light detection layer. Amorphous polysilicon can be used to form the red light detection layer to boost the efficiency of detecting red light.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: August 20, 2013
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Hsin-Chih Tai, Duli Mao, Vincent Venezia, Howard E. Rhodes
  • Publication number: 20130207212
    Abstract: A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element. The trench is positioned to impede a light path between the light emitting element and the light sensing element when the light path is internal to the semiconductor layer.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Gang Chen, Howard E. Rhodes
  • Patent number: 8502290
    Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 6, 2013
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • Patent number: 8497536
    Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: July 30, 2013
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Ashish Shah, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 8492865
    Abstract: An image sensor array includes a substrate layer, a metal layer, an epitaxial layer, a plurality of imaging pixels, and a contact dummy pixel. The metal layer is disposed above the substrate layer. The epitaxial layer is disposed between the substrate layer and the metal layer. The imaging pixels are disposed within the epitaxial layer and each include a photosensitive element for collecting an image signal. The contact dummy pixel is dispose within the epitaxial layer and includes an electrical conducting path through the epitaxial layer. The electrical conducting path couples to the metal layer above the epitaxial layer.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: July 23, 2013
    Assignee: OmniVision Technologies, Inc.
    Inventors: Vincent Venezia, Duli Mao, Hsin-Chih Tai, Yin Qian, Howard E. Rhodes
  • Patent number: 8482639
    Abstract: An imaging sensor pixel array includes a semiconductor substrate, a plurality of active pixels and at least one black reference pixel. The plurality of active pixels are disposed in the semiconductor substrate for capturing an image. Each of the active pixels includes a first region for receiving light including a p-n junction for accumulating an image charge and active pixel circuitry coupled to the first region to readout the image charge. The black reference pixel is also disposed within the semiconductor substrate for generating a black level reference value. The black reference pixel includes a second region for receiving light without a p-n junction and black pixel circuitry coupled to the photodiode region without the p-n junction to readout a black level reference signal.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: July 9, 2013
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hsin-Chih Tai, Vincent Venezia, Duli Mao, Howard E. Rhodes
  • Patent number: 8461692
    Abstract: A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 11, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes