Patents by Inventor Howard H. Smith
Howard H. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10467372Abstract: A method and system for implementing automated identification of optimal sense point (SP) and sector locations in various on-chip linear voltage regulator designs. A customized cost function is used along with predefined performance metrics to identify optimal SP and sector locations, under user-defined design constraints. The SP and sector locations are updated based on the identified optimization results, and the updated SP and sector locations are applied to an on-chip linear voltage regulator design to provide enhanced regulator performance and to ensure proper operation.Type: GrantFiled: July 31, 2017Date of Patent: November 5, 2019Assignee: International Business Machines CorporationInventors: Anurag P. Umbarkar, Erich C. Schanzenbach, Howard H. Smith, Raju Balasubramanian
-
Publication number: 20190034573Abstract: A method and system for implementing automated identification of optimal sense point (SP) and sector locations in various on-chip linear voltage regulator designs. A customized cost function is used along with predefined performance metrics to identify optimal SP and sector locations, under user-defined design constraints. The SP and sector locations are updated based on the identified optimization results, and the updated SP and sector locations are applied to an on-chip linear voltage regulator design to provide enhanced regulator performance and to ensure proper operation.Type: ApplicationFiled: July 31, 2017Publication date: January 31, 2019Inventors: Anurag P. Umbarkar, Erich C. Schanzenbach, Howard H. Smith, Raju Balasubramanian
-
Patent number: 9607118Abstract: A linear circuit simulator can be supplied with a linear power distribution model of an integrated circuit (IC) and two sets of voltage regulator equivalent resistances. The linear circuit simulator can then be used to calculate two voltages, at a sense point of the IC, corresponding to the two sets of voltage regulator equivalent resistances. The two sets of voltage regulator equivalent resistances and the two voltages at the IC sense point can be used to interpolate a slope of a resistance versus voltage curve of the linear power distribution model. The slope can be used to calculate an updated set of voltage regulator equivalent resistances, which can be used by the linear circuit simulator to calculate a set of performance metrics and an updated voltage at the sense point of the IC.Type: GrantFiled: April 19, 2016Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Raju Balasubramanian, Erich C. Schanzenbach, Howard H. Smith, Anurag P. Umbarkar
-
Patent number: 9582622Abstract: A linear circuit simulator can be supplied with a linear power distribution model of an integrated circuit (IC) and two sets of voltage regulator equivalent resistances. The linear circuit simulator can then be used to calculate two voltages, at a sense point of the IC, corresponding to the two sets of voltage regulator equivalent resistances. The two sets of voltage regulator equivalent resistances and the two voltages at the IC sense point can be used to interpolate a slope of a resistance versus voltage curve of the linear power distribution model. The slope can be used to calculate an updated set of voltage regulator equivalent resistances, which can be used by the linear circuit simulator to calculate a set of performance metrics and an updated voltage at the sense point of the IC.Type: GrantFiled: December 21, 2015Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Raju Balasubramanian, Erich C. Schanzenbach, Howard H. Smith, Anurag P. Umbarkar
-
Patent number: 7971171Abstract: The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density in the at least one interconnect to an effective local maximum current density limit of the at least one interconnect.Type: GrantFiled: May 20, 2008Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: Joachim Keinert, Howard H. Smith, Patrick M. Williams
-
Patent number: 7844435Abstract: An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.Type: GrantFiled: November 19, 2007Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Michael A. Bowen, Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin, Howard H. Smith, David J. Widiger
-
Publication number: 20090013290Abstract: The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal (UD) and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density (if,rms,R32) in the at least one interconnect to an effective local maximum current density limit (irms,max) of the at least one interconnect.Type: ApplicationFiled: May 20, 2008Publication date: January 8, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joachim Keinert, Howard H. Smith, Patrick M. Williams
-
Patent number: 7346877Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.Type: GrantFiled: April 20, 2006Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Howard H. Smith, Richard P. Underwood, Alan P. Wagstaff
-
Patent number: 7319946Abstract: New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.Type: GrantFiled: October 21, 2002Date of Patent: January 15, 2008Assignee: International Business Machines CorporationInventors: Michael A. Bowen, Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin, Howard H. Smith, David J. Widiger
-
Patent number: 7269806Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.Type: GrantFiled: April 20, 2006Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Howard H. Smith, Richard P. Underwood, Alan P. Wagstaff
-
Patent number: 7093206Abstract: A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.Type: GrantFiled: October 21, 2003Date of Patent: August 15, 2006Assignee: International Business Machines Corp.Inventors: Minakshisundaran B. Anand, Matthew S. Angyal, Alina Deutsch, Ibrahim M. Elfadel, Gerard V. Kopcsay, Barry J. Rubin, Howard H. Smith
-
Patent number: 7086026Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques: 1. A method for descending through hierarchy and dividing the design into a variable sized grid. 2. An algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location. 3. An algorithm to determine which grid locations are subject to harmful neighboring effects. 4. A method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.Type: GrantFiled: May 12, 2003Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Howard H. Smith, Richard P. Underwood, Alan P. Wagstaff
-
Patent number: 6963204Abstract: The present invention relates to a method for analyzing the noise prediction within one or more electrical circuits, wherein the electrical circuits have a power mesh grid distribution system that feeds power levels to the electrical circuits that are connected by signal wires. After identifying a driver and receiver electrical circuit to be analyzed, a power block is generated that is associated with the driver and receiver electrical circuit by partitioning an area of a power mesh grid distribution system into a power block that can be modeled with lossy transmission line techniques. Next, signal wires situated between the driver and receiver electrical circuits are partitioned into signal blocks that can be modeled with lossy transmission line techniques. Lastly, the power blocks and signal blocks associated with the electrical circuits are analyzed in order to predict the noise performance within the electrical circuits.Type: GrantFiled: April 6, 2004Date of Patent: November 8, 2005Assignee: International Business Machines CorporationInventors: Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin, Howard H. Smith
-
Publication number: 20040230926Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable.Type: ApplicationFiled: May 12, 2003Publication date: November 18, 2004Applicant: International Business Machines CorporationInventors: Christopher J. Berry, Howard H. Smith, Richard P. Underwood, Alan P. Wagstaff
-
Publication number: 20040078176Abstract: New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs:Type: ApplicationFiled: October 21, 2002Publication date: April 22, 2004Applicant: International Business Machines CorporationInventors: Michael A. Bowen, Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin, Howard H. Smith, David J. Widiger
-
Patent number: 6618843Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.Type: GrantFiled: June 29, 2001Date of Patent: September 9, 2003Assignee: International Business Machines CorporationInventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
-
Patent number: 6618844Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.Type: GrantFiled: June 29, 2001Date of Patent: September 9, 2003Assignee: International Business Machines CorporationInventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
-
Patent number: 6582012Abstract: A separator panel water management system is provided for a vehicle. The vehicle includes a separator panel positioned within an opening defined between a vehicle interior and a vehicle cargo box. The separator panel is pivotable between a closed position within the opening and an open position away from the opening to allow cargo to extend from the cargo box through the opening into the vehicle interior. A seal is positioned within the opening to seal the separator panel within the opening to prevent water leakage from the cargo box into the vehicle interior. A water management tray is positioned below the opening to receive any water which leaks past the seal into the vehicle interior. The water management tray has at least one channel formed therein to direct the water into at least one hole formed through the tray. A water discharge path is configured to receive water from the hole and to direct the water out of the vehicle interior.Type: GrantFiled: March 28, 2002Date of Patent: June 24, 2003Assignee: General Motors CorporationInventor: Howard H Smith
-
Patent number: 6546529Abstract: Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available.Type: GrantFiled: October 2, 2000Date of Patent: April 8, 2003Assignee: International Business Machines CorporationInventors: Allan H. Dansky, Michael A. Bowen, Peter J. Camporese, Alina Deutsch, Howard H. Smith
-
Patent number: D893625Type: GrantFiled: February 4, 2019Date of Patent: August 18, 2020Inventor: Howard H. Smith