Abstract: A routing program length method for positioning unit pins in a hierarchically designed VLSI chip first identifies unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the Incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units.

Abstract: A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures—due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.

Abstract: A method for identifying and positioning sub-optimally positioned unit pins in a hierarchically designed VSLI chip without modifying unit placement, comprising: generating a flat data file, generating a first pin log using the flat data file including data for unit pins and for macro pins of a net, generating a second pin log using the flat data file including data for macro pins of the net, determining a minimal net length using the first pin log and determining a minimum net length using the second pin log, calculating the difference between the minimal net length determined using the first ping log and the minimal net length determmed using the second pin log, identifying sub-optimally positioned unit pins by comparing the calculated difference to a threshold, and repositioning the identified sub-optimally positioned unit pins.

Abstract: A method for identifying unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units.

Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Abstract: An exemplary embodiment of the invention is a method of characterizing capacitances of a plurality of integrated circuit interconnects. The method includes coupling a first oscillator to a first integrated circuit interconnect and coupling a second oscillator to a second integrated circuit interconnect. The first oscillator is activated to characterize the sum of (i) coupling capacitance between the first integrated-circuit interconnect and the second integrated-circuit interconnect and (ii) ground capacitance between the first integrated-circuit interconnect and a ground. In addition, both of the first oscillator and the second oscillator are activated to characterize the ground capacitance between the first integrated-circuit interconnect and the ground.

Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Abstract: A fishing tackle improvement having the following embodiments: a tackle head larger in diameter or width on all sides than the tackle body behind it; an exterior body containing and protecting the interior parts during impact; a stationary hook anchor inside the end of the tackle body nearest the tackle head; a connecting screw threaded at both ends affixed to the tackle head at one end and tackle lift wedge at the other, causing both parts to move as one; a lift wedge possessing channels for the barbed end of the hooks to drop into, and lift fins that extend through the tackle body wall to prevent internal part rotation; a system of hook channels dropping inward from the exterior of the hook anchor and lift wedge, beside and below true center in a line off axis of true center; fins formed as part of the lift wedge that extend above the main body of the lift wedge in the same off center axis as the hook channels.

Abstract: A cutting tool is provided with a plurality of circular cutting blades of varying predetermined thicknesses to shear sections from rings made of precious metals. Each blade is formed with a notched perimeter to provide a pair of blade cutting edges. The blades are mounted on a spindle for rotation therewith, while the spindle is rotatably mounted in a plurality of cutting blocks which are affixed to a base in an alternating arrangement with the aforesaid blades. The cutting blocks define cutting edges so that rotation of the spindle causes the blade cutting edges formed by the notched perimeter to come into a simultaneous shearing relation with the cutting edges of the two adjacent cutting blocks. Further rotation of the spindle will shear out a section of a ring interposed in the notched perimeter of the blade. The tool is further provided with removable trays to catch sheared pieces of precious metals. Rotation of the spindle is accomplished through a conventional crank handle.

Abstract: A utensil for opening an oyster which also serves to cut the oyster umbilical cord and lift the oyster out of its shell. The utensil is fitted with a handle to which the blade is fixed, with the blade being formed of metal, preferably stainless steel. The blade is shaped with a curved spoon section serrated at opposed sides of the spoon for the severing of the oyster umbilical cord, with a knife section projecting along the axis of the blade, from the spoon.