Patents by Inventor Howard T. Olnowich

Howard T. Olnowich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5668948
    Abstract: A media streamer (10) includes at least one storage node (16, 17) for storing a digital representation of a video presentation. The Video presentation requires a time T to present in its entirety, and is stored as a plurality of N data blocks, each data block storing data corresponding approximately to a T/N period of the video presentation.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: September 16, 1997
    Assignee: International Business Machines Corporation
    Inventors: William Russell Belknap, Louise Irene Cleary, James W. Eldridge, Larry William Fitchett, Stephen G. Luning, Christopher S. Murray, Howard T. Olnowich, Ashok Raj Saxena, Karl David Schubert, Buddy Floyd Stansbury
  • Patent number: 5617547
    Abstract: An electronic switching and data transmission system for interconnecting a plurality of buses. A switching network interconnects several multi-drop buses using adapters to connect the buses to the switching network. The adapters implements hardware functions to appear to software as if all devices on the several buses were attached to a single large bus. The system permits higher speed transfer modes by eliminating multi-drop bus limitations.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: April 1, 1997
    Assignee: International Business Machines Corporation
    Inventors: James W. Feeney, John D. Jabusch, Robert F. Lusch, Howard T. Olnowich, George W. Wilhelm, Jr.
  • Patent number: 5612953
    Abstract: A generic network device for performing parallel or serial communications amongst multiple nodes over switching networks. An aspect is the adaptation of standard or proprietary serial interfaces using optical or electrical transmission to interface to the parallel switch. Converted serial data is routed to the selected destination through the parallel switch network. At the destination the data is converted back to a serial optical or electrical interface/protocol. Any number of different serial protocols can interface with the same parallel switch network allowing every node of the parallel system to send and receive messages in its native protocol. The switch enables generic networks forming a computer system with heterogeneous or homologous nodes.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: March 18, 1997
    Assignee: International Business Machines Corporation
    Inventor: Howard T. Olnowich
  • Patent number: 5610953
    Abstract: A receiver device is provided with a low latency recovery apparatus for recovering serially transmitted digital data. The receiver device operates asynchronously in respect to a transmitting device. The low latency recovery apparatus synchronizes the receiver device in one clock time to support throughput of high speed transmission messages received from interconnection networks or interface cables. A metastability proof latch is provided. A synchronization method provides individual alignment for each incoming message. There is instantaneous response to back-to-back messages from different sources. Synchronization is accomplished in the receiving device by implementing a clocking system capable of generating N phase-shifted clocks all operating at the same frequency as the incoming data. The N clocks are shifted an approximately equal amount in relation to each other.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: March 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: Robert Betts, Howard T. Olnowich
  • Patent number: 5542048
    Abstract: A multi-stage circuit switched network for improving connection establishment using intelligent switching devices. As a transmission makes its way through the network stages, the probability of connecting to a destination increases, i.e., the chance of encountering a blocked device output is decreased. This is opposite of most traditional networks, whose probability for success diminishes with every stage in the connection sequence.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: July 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Howard T. Olnowich, Jehoshua Bruck, James W. Feeney, Eli Upfal
  • Patent number: 5535373
    Abstract: A generic network device includes a serial line switching apparatus for performing either parallel or serial communications amongst multiple nodes over switching networks. An aspect includes the adaptation of standard and proprietary serial interfaces using either optical or electrical transmission media to interface to a parallel switch. The converted serial data is routed to the selected destination through the parallel switch network, where it is received and converted back into a serial optical or electrical interface/protocol. Thus, the combination of the switching adapter and an ALLNODE parallel switching network make it feasible for serial message data to be switched and routed to various destinations. Further flexibility is provided which permits the switching adapter to be personalized to support any one of a number of standard and proprietary serial protocols. A personalization PROM specifies the particular serial protocol that each individual adapter is to support.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: July 9, 1996
    Assignee: International Business Machines Corporation
    Inventor: Howard T. Olnowich
  • Patent number: 5495474
    Abstract: A modularly expandable switch-based planar apparatus for insertable multiple bus-based processor cards and/or expansion cards and interconnecting the cards via a multi-stage switch network which resides on the planar apparatus. The cards require no modification or change of any kind, since the connection to the planar apparatus is made as if the planar apparatus contained the standard MicroChannel interconnection. The planar apparatus implements bus converter units to convert the standard bus interface provided by the cards to the switch network interface, so that functions provided by the cards can communicate in parallel over the switch network.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: February 27, 1996
    Assignee: International Business Machines Corp.
    Inventors: Howard T. Olnowich, Michael H. Fisher, Robert F. Lusch, Michael A. Maniguet, Omar A. Saiyid
  • Patent number: 5465333
    Abstract: An apparatus is disclosed for processing information including a bus, a controller circuit, the controller circuit being configured to control transfer of information over the bus, and a slave circuit. The slave circuit includes a slave timing circuit which variably generates a ready signal indicating when the slave can accept data to allow the slave circuit to function in computer systems having different bus speeds. The controller circuit and the slave circuit exchange information via the bus at a speed controlled by the ready signal.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: November 7, 1995
    Assignee: International Business Machines Corporation
    Inventor: Howard T. Olnowich
  • Patent number: 5444705
    Abstract: A high priority path is added to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as an output port becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: August 22, 1995
    Assignee: International Business Machines Corp.
    Inventors: Howard T. Olnowich, Thomas N. Barker, Peter M. Kogge, Gilbert C. Vandling, III
  • Patent number: 5408646
    Abstract: Disclosed is a new torus switch with low latency performance improves torus network connection time by trying multipaths in one single high speed operation. This multipath approach can be directed at establishing a connection between two specific nodes over various alternate routes simultaneously. If only one route is available, the multipath approach will find that path instantaneously and establish the desired connection with minimal latency. If several links are available, the multipath method establishes the desired connection over only one of the available links and leaves the other options free to be used by other connections. In addition, routing at intermediate torus network stages improves over the wormhole approach.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: April 18, 1995
    Assignee: International Business Machines Corp.
    Inventors: Howard T. Olnowich, Arthur R. Williams
  • Patent number: 5404461
    Abstract: A broadcast/switching apparatus makes input port to output port connections on a requested basis quickly and dynamically in a standard mode from any one of the input ports to any one of the output ports, in a multi-cast mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously, using a new asynchronous approach to resolve either broadcast or multi-cast contention among input ports. The normal mode of the broadcast/switch apparatus requires absolutely no synchronization among any of the input and output ports which interface to the apparatus. The broadcast/switch apparatus also incorporates a new accept protocol that enables a positive feedback indication to be returned to the sender of a multi-cast or broadcast operation to inform it that the multi-cast or broadcast transmission was correctly received by all elements involved in the multi-cast or broadcast.
    Type: Grant
    Filed: August 21, 1991
    Date of Patent: April 4, 1995
    Assignee: International Business Machines Corp.
    Inventors: Howard T. Olnowich, Robert F. Lusch, John D. Jabusch
  • Patent number: 5404537
    Abstract: A method and apparatus for implementing intelligent priority functions at individual switching apparatus devices which comprise switching networks. The intelligent switching functions are capable of operating in real time systems with high efficiency. The switching apparatus has the capability at each stage of the network to make and/or break connections on a priority basis. If a connection is requested at a switch stage and the connection is being used by a lower priority device, the low priority connection is interrupted (broken) and the requested higher priority connection is established. After the high priority connection has completed its usage of the connection, the high priority connection is broken and the lower priority connection is re-established.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: April 4, 1995
    Assignee: International Business Machines Corp.
    Inventors: Howard T. Olnowich, David B. Kirk
  • Patent number: 5384773
    Abstract: Disclosed is multi-media switching apparatus for performing digital, analog, and/or optical communications amongst multiple nodes over switching networks. The key aspect of the present invention is the full parallel aspect of the switching apparatus which supports n simultaneously, low-latency connections, where n is the number of functional elements interconnected by the switching network. Any of the n simultaneous transmissions can be digital, analog, or optical in any proportion. In addition, the present invention can also serve as a high-speed distributed controller for the purpose of of selecting analog or optical switches for information transfer between elements of the system.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: January 24, 1995
    Assignee: International Business Machines Corp.
    Inventors: Howard T. Olnowich, John D. Jabusch, Robert F. Lusch, Michael A. Maniguet
  • Patent number: 5365228
    Abstract: A SYNC-NET apparatus synchronizes processor nodes of a parallel system over a multi-stage communication network that normally transmits data between nodes as point-to-point communications, broadcast, multi-cast, or multi-sender transfers. The apparatus performs priority driven arbitration over the network to resolve conflicts amongst multiple processing nodes simultaneously requesting use of the multi-stage network for performing barrier synchronization over the network in relation to the same or different barriers. The apparatus uses a special capability multi-stage network that can support only one barrier synchronization operation at any given time, and which makes it necessary to perform a priority arbitration to determine which barrier synchronization gets performed first, second, and so on. Any number of processor nodes can arbitrate simultaneously for use of the barrier synchronization facilities, and the arbitration will be resolved quickly and consistently by selecting the highest priority requestor.
    Type: Grant
    Filed: August 21, 1991
    Date of Patent: November 15, 1994
    Assignee: International Business Machines Corporation
    Inventors: Philip L. Childs, Howard T. Olnowich, Joseph F. Skovira
  • Patent number: 5345229
    Abstract: Disclosed is a method and apparatus for improving the performance and connection establishing capability of multi-stage switching networks by providing additional intelligent features in the individual switching apparatus devices at each stage of the network. The invention method is particularly effective in asynchronous circuit-switched networks. The most important feature to be added is adaptivity of the switching apparatus; where adaptivity means the ability of each switching element to determine for itself which of several optional alternate paths to try at each stage of the network based on availability. This is a better approach because it brings the decision directly to the switching apparatus involved, which has the data required to make an intelligent path selection decision to circumvent blocking in the multi-stage network.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: September 6, 1994
    Assignee: International Business Machines Corporation
    Inventors: Howard T. Olnowich, Jehoshua Bruck, Marc Snir, Eli Upfal
  • Patent number: 5263172
    Abstract: A computer system which includes a synchronous digital, multibit system bus having a clock path, a master speed indicator path and a slave speed indicator path, a bus control circuit which provides first and second clocks to the clock path of the bus, the second clock having a different frequency than the first clock, and a master circuit and a slave circuit connected to the system bus. The master circuit includes master speed indication circuitry which provides a master speed indicator indicating the operating speed of the master circuit to the master speed indicator path. The slave circuit includes slave speed indication circuitry which provides a slave speed indicator indicating the operating speed of the slave circuit to the slave speed indicator path. The bus controller provides the second clock when the master speed indicator and the slave speed indicator indicate that the master circuit and the slave circuit both may function at the different frequency of the second clock.
    Type: Grant
    Filed: April 16, 1990
    Date of Patent: November 16, 1993
    Assignee: International Business Machines Corporation
    Inventor: Howard T. Olnowich
  • Patent number: 5250943
    Abstract: A GVT-NET apparatus for all processor nodes of a parallel system for repetitive calculation of the latest global virtual time (GVT) value quickly and accurately over the communication multi-stage network (NET) that normally transmits data between nodes as point-to-point communications, broadcast, multi-cast, or multi-sender transfers. For multi-processor synchronization, each processing node can free-run and keep track of its local time and synchronize with the other processors by polling all processors to determine the minimal of the individual local times and indicate how far the entire job has progressed. The multi-sender and multi-cast functions in the multi-stage network enable every node attached to the multi-stage network to participate in one common and simultaneous GVT calculation, where each processor node can simultaneously transmit the inverse of its local time to the network and at the same time monitor the network output.
    Type: Grant
    Filed: August 21, 1991
    Date of Patent: October 5, 1993
    Assignee: International Business Machines Corporation
    Inventors: Philip L. Childs, Howard T. Olnowich, Joseph F. Skovira
  • Patent number: 5043877
    Abstract: An apparatus for transferring data between a computer system having a first architecture and a slave element having a second architecture. The apparatus includes a first connector corresponding to the first architecture, a second connector corresponding to the second architecture, and conversion circuitry located between the first connector and the second connector. The conversion circuitry converts signals corresponding to the first architecture to signals corresponding to the second architecture and signals corresponding to the second architecture to signals corresponding to the first architecture.
    Type: Grant
    Filed: October 12, 1990
    Date of Patent: August 27, 1991
    Assignee: International Business Machines Corp.
    Inventors: Erwin R. Berger, Howard T. Olnowich
  • Patent number: 4701842
    Abstract: In a pipelined instruction execution system including a microstore for storing sequences of microinstruction addresses associated with each macroinstruction, a nanostore for randomly storing unique microinstructions, and an execution unit for executing the microinstructions, a no-op/prefetch apparatus, according to the present invention, prevents a microinstruction address, stored in the microstore, from accessing the nanostore and forces a no-op address into the nanostore when the execution unit executes a conditional microbranch instruction. A no-op microinstruction, corresponding to the no-op address, is retrieved from the nanostore and is executed in the execution unit.
    Type: Grant
    Filed: October 4, 1985
    Date of Patent: October 20, 1987
    Assignee: International Business Machines Corporation
    Inventor: Howard T. Olnowich
  • Patent number: 4493026
    Abstract: A cache memory for a data processing system having a tag array in which each tag word represents a predetermined plurality or block group of consecutively addressable data block locations in a data array. The lower order set address bits concurrently access the tag word and its associated group of block locations in the data array while individual blocks within the group are accessed by supplemental block bits. Each tag word read out must compare equal with the high order bits of the address and an accompanying validity bit for each block location in its group must be set in order to effect a hit. Also described are circuits for writing into the cache and adapting the cache to a multi-cache arrangement.
    Type: Grant
    Filed: May 26, 1982
    Date of Patent: January 8, 1985
    Assignee: International Business Machines Corporation
    Inventor: Howard T. Olnowich