Abstract: A substitute box includes a target input terminal, an obfuscation input terminal, a first output terminal and a second output terminal. The target input terminal is configured to receive a target input data. The obfuscation input terminal is configured to receive an obfuscation input data unrelated to a plaintext. The first output terminal is configured to output a first output data. The second output terminal is configured to output a second output data associated with the first output data. The first output data and the second output data are generated according to both the target input data and the obfuscation input data.

Abstract: A substitute box includes a target input terminal, an obfuscation input terminal, a first output terminal and a second output terminal. The target input terminal is configured to receive a target input data. The obfuscation input terminal is configured to receive an obfuscation input data unrelated to a plaintext. The first output terminal is configured to output a first output data. The second output terminal is configured to output a second output data associated with the first output data. The first output data and the second output data are generated according to both the target input data and the obfuscation input data.

Abstract: An encoding method includes: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.

Abstract: The present invention discloses an encoder, a decoder, an encoding method and a decoding method based on Low-Density Parity-Check (LDPC) code. The encoding method comprises: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.

Abstract: The present disclosure provides a decoding system and method. The decoding system comprises a first decoder and a second decoder. The first decoder is configured to generate an intermediate decoding data by decoding a code data. The second decoder, coupled to the first decoder, wherein the second decoder is configured to generate a plain data by decoding the intermediate decoding data.

Abstract: The present disclosure provides a decoding system and method. The decoding system comprises a first decoder and a second decoder. The first decoder is configured to generate an intermediate decoding data by decoding a code data. The second decoder, coupled to the first decoder, wherein the second decoder is configured to generate a plain data by decoding the intermediate decoding data.

Abstract: A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.

Abstract: A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.

Abstract: A cracking method for cracking a secret key of an encrypting device includes: building up a leakage model for the encrypting device; performing a mathematical calculation on the leakage model, according to a plurality of sets of input data, to generate a mathematical model; generating a plurality of sets of hypothesized keys; generating a plurality of sets of simulation data corresponding to the hypothesized keys using the mathematical model; providing the input data for the encrypting device and detecting a plurality of sets of leakage data generated by the encrypting device; performing the mathematical calculation on the leakage data to generate calculated data; determining a correlation between each of the simulation data and the calculated data; and determining one of the hypothesized keys to be consistent with the secret key according to the correlation.

Abstract: A cracking method for cracking a secret key of an encrypting device includes: building up a leakage model for the encrypting device; performing a mathematical calculation on the leakage model, according to a plurality of sets of input data, to generate a mathematical model; generating a plurality of sets of hypothesized keys; generating a plurality of sets of simulation data corresponding to the hypothesized keys using the mathematical model; providing the input data for the encrypting device and detecting a plurality of sets of leakage data generated by the encrypting device; performing the mathematical calculation on the leakage data to generate calculated data; determining a correlation between each of the simulation data and the calculated data; and determining one of the hypothesized keys to be consistent with the secret key according to the correlation.

Abstract: An operating method of a memory controller, for a memory device including a plurality of cells, includes steps of: checking states of the cells; marking at least one specific bit-channel according to the states of the cells; and performing an uneven wear leveling scheme on at least one target cell storing messages from the at least one specific bit-channel, such that the wear level of the at least one target cell is different from other cells.

Abstract: A data analysis system includes a modeling unit, a feature-extraction unit, a processing unit and an output unit. The modeling unit creates a prediction model by a machine learning algorithm according to training data. The feature-extraction unit extracts a plurality of fragment of feature data of input data, and classifies the feature data into a plurality of groups. The processing unit obtains a probability of the input data corresponding to the prediction model by the machine learning algorithm according to the feature of one of the groups, and determines the probability. When the probability is less than a predetermined value, the processing unit uses another feature data corresponding to another group which is not used to renew the probability of the input data corresponding to the prediction model through the machine learning algorithm. When the probability is greater than or equal to the predetermined value, the processing unit classifies the input data. The output unit outputs a classification result.

Abstract: A data analysis system includes a modeling unit, a feature-extraction unit, a processing unit and an output unit. The modeling unit creates a prediction model by a machine learning algorithm according to training data. The feature-extraction unit extracts a plurality of fragment of feature data of input data, and classifies the feature data into a plurality of groups. The processing unit obtains a probability of the input data corresponding to the prediction model by the machine learning algorithm according to the feature of one of the groups, and determines the probability. When the probability is less than a predetermined value, the processing unit uses another feature data corresponding to another group which is not used to renew the probability of the input data corresponding to the prediction model through the machine learning algorithm. When the probability is greater than or equal to the predetermined value, the processing unit classifies the input data. The output unit outputs a classification result.

Abstract: A data storage device is in communication with a host through a bus. The data storage device includes a storage medium and a controlling unit. The controlling unit is connected with the host and the storage medium for receiving an analysis data, or storing a write data into the storage medium or retrieving a read data from the storage medium to the host according to a command from the host. The controlling unit includes an arithmetic logic unit. The arithmetic logic unit has a built-in algorithm for analyzing and processing the analysis data, the write data or the read data, thereby generating an analysis result. Moreover, the algorithm may be updated or expanded by the host.

Abstract: An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.

Abstract: An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.

Abstract: The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G1(x)); next, dividing M1(x)x4 by G1(x) to obtain a first remainder polynomial (R1(x)); next, generating a second code generator polynomial (G2(x)) from G1(x); next, generating a third polynomial (M3(x)); next, dividing M3(x)x4 by G2(x) to obtain a second remainder polynomial (R2(x)); next, performing an adding procedure to R1(x) and R2(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).

Abstract: A two-dimensional array is stored in a first storage memory. A data accessing direction of the first storage memory is in a row direction. A method for reading data in the two-dimensional array in a column direction contains reading a plurality of data sets in the array from the first storage memory; performing a calculating operation on a first data set of the plurality of data sets; storing remaining data sets of the plurality of data sets into a second storage memory; and sequentially reading and applying the calculating operation on the remaining data sets stored in the second storage memory.

Abstract: The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)).

Abstract: The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution interleaving on data symbol comprises a memory, an original address generator, and a storage address generator which generates an original address. The storage address generator generates the storage address of each of the stored plural data symbols in the memory according to the original address and a first predetermined sequence, and each of the convolution interleaved data symbols is stored in the memory according to the storage address; furthermore, all stored data symbols in the memory are configured into a circular structure.