Patents by Inventor Hsiang-Huan Lee

Hsiang-Huan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930552
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
  • Publication number: 20200091068
    Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Inventors: Chao-Hsien Peng, Hsiang-Huan Lee, Shau-Lin Shue
  • Publication number: 20200051857
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
  • Patent number: 10490497
    Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 10453746
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
  • Patent number: 10354954
    Abstract: The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a metal projection protruding outward from an upper surface of the metal body. A dielectric layer is disposed over the substrate and surrounds the metal body and the metal projection. A barrier layer separates the metal body and the metal projection from the dielectric layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee, Tien-I Bao
  • Patent number: 10121698
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Publication number: 20180301416
    Abstract: The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a metal projection protruding outward from an upper surface of the metal body. A dielectric layer is disposed over the substrate and surrounds the metal body and the metal projection. A barrier layer separates the metal body and the metal projection from the dielectric layer.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 18, 2018
    Inventors: Chih-Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee, Tien-I Bao
  • Publication number: 20180233406
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 16, 2018
    Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
  • Patent number: 10020259
    Abstract: The present disclosure relates to a method for forming an interconnect structure. In some embodiments, the method may be performed by forming an opening within a sacrificial layer. The sacrificial layer is over a substrate. A conductive material is formed within the opening and over the sacrificial layer. The conductive material within the opening defines a conductive body. The conductive material is patterned to define a conductive projection extending outward from the conductive body. The sacrificial layer is removed and a dielectric material is formed surrounding the conductive body and the conductive projection.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee, Tien-I Bao
  • Patent number: 10014175
    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao, Tsai-Sheng Gau, Yung-Hsu Wu
  • Patent number: 9947583
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
  • Patent number: 9892933
    Abstract: A method embodiment for patterning a semiconductor device includes forming a plurality of mandrels over a substrate, and forming a multilayer spacer layer over the plurality of mandrels. The multilayer spacer layer is formed by conformably depositing a spacer layer over the plurality of mandrels and treating the spacer layer with plasma. The plurality of mandrels is exposed by etching a top portion of the multilayer spacer layer, thereby forming a multilayer spacer.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Hsiang-Huan Lee, Shau-Lin Shue
  • Publication number: 20180012761
    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 11, 2018
    Inventors: Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao, Tsai-Sheng Gau, Yung-Hsu Wu
  • Patent number: 9842767
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Han Lee, Tz-Jun Kuo, Chien-Hsin Ho, Hsiang-Huan Lee
  • Patent number: 9837310
    Abstract: A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Chi-Liang Kuo, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9818644
    Abstract: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Yi Yang, Hsi-Wen Tien, Ming-Han Lee, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9773676
    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao, Tsai-Sheng Gau, Yung-Hsu Wu
  • Publication number: 20170236750
    Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Shin-Yi Yang, Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming-Han Lee
  • Patent number: 9728503
    Abstract: In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsien Peng, Chi-Liang Kuo, Ming-Han Lee, Hsiang-Huan Lee, Shau-Lin Shue