Patents by Inventor Hsiang-Ming Huang
Hsiang-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937515Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.Type: GrantFiled: August 9, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11923405Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.Type: GrantFiled: May 23, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 10568663Abstract: The present invention discloses a spinal surgical instrument and a method of guiding thereof. The spinal surgical instrument is operated with a precedent device. The precedent device includes at least one guiding unit. The spinal surgical instrument includes an operating element, an extending element, a handling element and a guide element. One end of the extending element connects to the operating element. The other end of the extending element connects to the handling element. The guide element is disposed on the extending element and includes at least one guide hole. The operating element is guided to the precedent device by the passing of the guide hole along the guiding unit.Type: GrantFiled: September 12, 2017Date of Patent: February 25, 2020Assignee: Wiltrom Co., Ltd.Inventors: Yi-Chun Su, Sherwin Hua, Hsiang-Ming Huang, Huang-Chien Liang, Chieh-Feng Lu, Huang-Chi Chen
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Publication number: 20200008841Abstract: The present invention discloses a spinal surgical instrument and a method of guiding thereof. The spinal surgical instrument is operated with a precedent device. The precedent device includes at least one guiding unit. The spinal surgical instrument includes an operating element, an extending element, a handling element and a guide element. One end of the extending element connects to the operating element. The other end of the extending element connects to the handling element. The guide element is disposed on the extending element and includes at least one guide hole. The operating element is guided to the precedent device by the passing of the guide hole along the guiding unit.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Inventors: Yi-Chun SU, Sherwin HUA, Hsiang-Ming HUANG, Huang-Chien LIANG, Chieh-Feng LU, Huang-Chi CHEN
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Publication number: 20180070987Abstract: The present invention discloses a spinal surgical instrument and a method of guiding thereof. The spinal surgical instrument is operated with a precedent device. The precedent device includes at least one guiding unit. The spinal surgical instrument includes an operating element, an extending element, a handling element and a guide element. One end of the extending element connects to the operating element. The other end of the extending element connects to the handling element. The guide element is disposed on the extending element and includes at least one guide hole. The operating element is guided to the precedent device by the passing of the guide hole along the guiding unit.Type: ApplicationFiled: September 12, 2017Publication date: March 15, 2018Inventors: Yi-Chun SU, Sherwin HUA, Hsiang-Ming HUANG, Huang-Chien LIANG, Chieh-Feng LU, Huang-Chi CHEN
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Patent number: 8993342Abstract: A magnetic separation unit is provided, including a first member made of non-magnetic materials comprising a trench extending within the first member and a second member made of magnetic materials including a protrusion portion protruding over a surface of the second member, wherein the first member connects the second member such that the trench functions as a fluid channel formed between the first and second members, and the protrusion portion of the second member is contained by the trench of the first member.Type: GrantFiled: June 13, 2011Date of Patent: March 31, 2015Assignee: Industrial Technology Research InstituteInventors: Mean-Jue Tung, Yu-Ting Huang, Li-Kou Chen, Yi-Shan Lin, Hsiang-Ming Huang, Shinn-Zong Lin, Woei-Cherng Shyu, Hsiao-Jung Wang
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Publication number: 20130119530Abstract: A thermally enhanced packaging structure includes a chip carrier; a high power chip disposed on the chip carrier; a molding compound covering the high power chip; a heat dissipating layer disposed on the molding compound, wherein the heat dissipating layer comprises a plurality of carbon nanocapsules (CNCs); and a non-fin type heat dissipating device, disposed either on the heat dissipating layer or between the molding compound and the heat dissipating layer. The molding compound can also comprise a plurality of CNCs.Type: ApplicationFiled: August 17, 2012Publication date: May 16, 2013Applicant: CHIPMOS TECHNOLOGIES INC.Inventors: AN HONG LIU, David Wei Wang, Shi Fen Huang, Yi Chang Lee, Hsiang Ming Huang
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Publication number: 20130069228Abstract: A flip-chip package structure comprising a substrate, a chip, a bump structure and a solder resist is provided. The substrate has a circuit layer disposed on the surface thereof. The chip comprises a central region and two edge regions disposed on the two sides of the central region. The bump structure is disposed on the central region of the chip and faces the substrate. The solder resist is disposed on the substrate to partially cover the circuit layer. The chip is electrically connected to the substrate by the bump structure, and the solder resist is adapted to come into contact with the two edge regions of the chip to support the chip with the bump structure when the chip is disposed on the substrate.Type: ApplicationFiled: July 26, 2012Publication date: March 21, 2013Inventors: An-Hong LIU, Hung-Hsin Liu, Jar-Dar Yang, Chi-Chia Huang, Yi-Chang Lee, Hsiang-Ming Huang
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Publication number: 20130049787Abstract: The present invention provides a method of testing a stacked semiconductor device structure. This method includes the following steps: providing a testing board having a plurality of testing points and a probe card; providing a substrate which is disposed on the testing board; providing a plurality of semiconductor devices; mounting and electrically connecting a first one of the semiconductor devices onto the substrate; mounting and electrically connecting a second one of the semiconductor devices onto the first one of the semiconductor devices; keeping the probe card in contact with the second one of the semiconductor devices for electrical testing; and repeating the steps of mounting and testing of the semiconductor devices until all of the semiconductor devices are tested. This method can ensure the integrity of electrical interconnections between the semiconductor devices of the stacked structure.Type: ApplicationFiled: April 12, 2012Publication date: February 28, 2013Inventors: Chi-Ming YI, An-Hong Liu, Hsiang-Ming Huang, Yi-Chang Lee
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Publication number: 20120255913Abstract: A magnetic separation unit is provided, including a first member made of non-magnetic materials comprising a trench extending within the first member and a second member made of magnetic materials including a protrusion portion protruding over a surface of the second member, wherein the first member connects the second member such that the trench functions as a fluid channel formed between the first and second members, and the protrusion portion of the second member is contained by the trench of the first member.Type: ApplicationFiled: June 13, 2011Publication date: October 11, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Mean-Jue Tung, Yu-Ting Huang, Li-Kou Chen, Yi-Shan Lin, Hsiang-Ming Huang, Shinn-Zong Lin, Woei-Cherng Shyu, Hsiao-Jung Wang
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Patent number: 8269352Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: GrantFiled: January 12, 2011Date of Patent: September 18, 2012Assignee: Chipmos Technologies Inc.Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Patent number: 8269351Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: GrantFiled: January 12, 2011Date of Patent: September 18, 2012Assignee: Chipmos Technologies Inc.Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Patent number: 8264068Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: GrantFiled: January 12, 2011Date of Patent: September 11, 2012Assignee: Chipmos Technologies Inc.Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Publication number: 20110309495Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: ApplicationFiled: January 12, 2011Publication date: December 22, 2011Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Publication number: 20110309496Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: ApplicationFiled: January 12, 2011Publication date: December 22, 2011Inventors: David Wei WANG, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Publication number: 20110309497Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: ApplicationFiled: January 12, 2011Publication date: December 22, 2011Inventors: David Wei WANG, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Publication number: 20110291268Abstract: A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface.Type: ApplicationFiled: August 16, 2010Publication date: December 1, 2011Inventors: David Wei WANG, An-Hong Liu, Hsiang-Ming Huang, Yi-Chang Lee
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Publication number: 20110291267Abstract: A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface.Type: ApplicationFiled: August 16, 2010Publication date: December 1, 2011Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Yi-Chang Lee
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Patent number: 7973310Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.Type: GrantFiled: July 10, 2009Date of Patent: July 5, 2011Assignee: Chipmos Technologies Inc.Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho
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Patent number: 7906333Abstract: A surface modification method of polysaccharide, the modified polysaccharide, and a method of culturing and recovery cells using the same are provided. The surface modification method of polysaccharide comprises (a) immersing a polysaccharide material in an acid, (b) immersing the polysaccharide material in an acidic solution containing a protein, and (c) immersing the polysaccharide material in an alkaline solution containing bivalent metal ions.Type: GrantFiled: March 21, 2006Date of Patent: March 15, 2011Assignee: Industrial Technology Research InstituteInventors: Chun-Jen Liao, Yung-chih Wu, Chen-Chi Tsai, Hsiang-Ming Huang, Yuan-Hua Hsu, Shu-Fang Chiang