Patents by Inventor Hsie-Chia Chang

Hsie-Chia Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031954
    Abstract: A data transmitting method using an LDPC code as an error correction code is provided. The method includes providing a parity check matrix of LDPC code, wherein the size of the parity check matrix is (m1+m2)×(n1+n2); in a sending side, encoding an input data of K bits with a encoder to generate a first block code of (n1+n2) bits, according to the parity check matrix; through a transmitting channel, sending n1 bits of the first block code from the sending side to a receiving side, wherein n2 bits of the first block code are not transmitted; and receiving the n1 bits of the first block code in the receiving side, and using the parity check matrix to perform a decoding algorithm to the received first block code to iterative decodes a second block code of (n1+n2) bits with a decoder. Furthermore, a data decoding method thereof is also provided.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 8, 2021
    Assignee: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Shu Lin, Yen-Chin Liao
  • Patent number: 10886944
    Abstract: A low-density parity-check code scaling method is disclosed. The method includes following steps: obtaining the original low-density parity-check matrix; forming the permutation matrices with the random row shift or the random column shift to the identity matrix; replacing the component codes by the permutation matrices and the all-zero matrix to form the extended low-density parity-check matrix; adjusting the code length and the code rate to form the global coupled low-density parity-check matrix; and outputting the global coupled low-density parity-check code.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 5, 2021
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsie-Chia Chang, Yen-Chin Liao, Shu Lin
  • Publication number: 20200099394
    Abstract: A low-density parity-check code scaling method is disclosed. The method includes following steps: obtaining the original low-density parity-check matrix; forming the permutation matrices with the random row shift or the random column shift to the identity matrix; replacing the component codes by the permutation matrices and the all-zero matrix to form the extended low-density parity-check matrix; adjusting the code length and the code rate to form the global coupled low-density parity-check matrix; and outputting the global coupled low-density parity-check code.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: HSIE-CHIA CHANG, YEN-CHIN LIAO, SHU LIN
  • Patent number: 10523239
    Abstract: A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: December 31, 2019
    Assignee: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Shu Lin, Yen-Chin Liao
  • Publication number: 20190319640
    Abstract: A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.
    Type: Application
    Filed: May 21, 2018
    Publication date: October 17, 2019
    Applicant: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Shu Lin, Yen-Chin Liao
  • Publication number: 20190319638
    Abstract: A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Applicant: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Shu Lin, Yen-Chin Liao
  • Patent number: 10326586
    Abstract: An encryption/decryption apparatus and a power analysis protecting method thereof are provided. The encryption/decryption apparatus adapted to perform encryption/decryption operation on digital data includes a data encryption/decryption unit, a random number generator, and a power analysis protecting circuit. The data encryption/decryption unit receives the digital data and performs an encryption/decryption operation on the digital data. The random number generator is used to generate random number data, the random number data has N bits, and N is a positive integer. The power analysis protecting circuit generates M kinds of power signals having different levels according to each bit data of the random number data when the random number data is received by the power analysis protecting circuit, and M is equal to the Nth power of 2.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: June 18, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Chun-Yuan Yu, Szu-Chi Chung, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee
  • Publication number: 20190164068
    Abstract: A method of building a decoding status prediction system is provided. Firstly, plural read records are collected during read cycles of a flash memory. Then, the plural read records are classified into read records with a first read result and read records with a second read result. Then, a first portion of the read records with the first read result are divided into K0 groups according to a clustering algorithm, and a second portion of the read records with the second read result are divided into K1 groups according to the clustering algorithm. Then, the read records of the K0 groups and the K1 groups are used to train prediction models. Consequently, K0×K1 prediction models are generated. Then, the prediction models are combined as a prediction database.
    Type: Application
    Filed: February 1, 2018
    Publication date: May 30, 2019
    Inventors: Yen-Chin LIAO, Ching-Hui Huang, Shih-Jia Zeng, Hsie-Chia Chang
  • Patent number: 10128982
    Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N?K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q?K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q?K frozen bits are allocated to the N?K frozen bit-channels and the q additional frozen bit-channels.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 13, 2018
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Ming Huang, Hsiang-Pang Li, Hsie-Chia Chang
  • Patent number: 10110251
    Abstract: A method and a system for data transmission are provided. The method includes: determining a size of a first block and a first degree distribution for a first data transmission according to a parameter which is related to a hardware specification of a receiving node; determining a channel loss rate of a channel between a sending note and the receiving node when completing the first data transmission; determining a size of a second block and a second degree distribution for a second data transmission according to the channel loss rate; and performing, by the sending node and the receiving node, the second data transmission according to the size of the second block and the second degree distribution.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: October 23, 2018
    Assignee: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Kuo-Kuang Yen, Yen-Chin Liao
  • Patent number: 10103841
    Abstract: A turbo decoder system decodes L-length digital data consisting of a systematic code and 1st and 2nd parity check codes, and includes a trellis controller obtaining the ratio of the bit-number Ep of the 1st/2nd parity check code to the bit-number D of an original systematic code and generating, based on the code rate of the digital data, a trellis control output indicating a target decoding trellis, which is selected by a turbo decoder to perform decoding operations. A zero-patch module patches zeros into the systematic code, and patches, based on the value of Ep/D, one or more zeros into the 1st/2nd parity check code so that parity check bits of the 1st/2nd parity check code and the zero-bit(s) form a periodically depunctured parity check code.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: October 16, 2018
    Assignee: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Chen-Yang Lin
  • Publication number: 20180062789
    Abstract: A turbo decoder system decodes L-length digital data consisting of a systematic code and 1st and 2nd parity check codes, and includes a trellis controller obtaining the ratio of the bit-number Ep of the 1st/2nd parity check code to the bit-number D of an original systematic code and generating, based on the code rate of the digital data, a trellis control output indicating a target decoding trellis, which is selected by a turbo decoder to perform decoding operations. A zero-patch module patches zeros into the systematic code, and patches, based on the value of Ep/D, one or more zeros into the 1st/2nd parity check code so that parity check bits of the 1st/2nd parity check code and the zero-bit(s) form a periodically depunctured parity check code.
    Type: Application
    Filed: February 22, 2017
    Publication date: March 1, 2018
    Inventors: Hsie-Chia CHANG, Chen-Yang LIN
  • Publication number: 20180048331
    Abstract: A method and a system for data transmission are provided. The method includes: determining a size of a first block and a first degree distribution for a first data transmission according to a parameter which is related to a hardware specification of a receiving node; determining a channel loss rate of a channel between a sending note and the receiving node when completing the first data transmission; determining a size of a second block and a second degree distribution for a second data transmission according to the channel loss rate; and performing, by the sending node and the receiving node, the second data transmission according to the size of the second block and the second degree distribution.
    Type: Application
    Filed: October 12, 2016
    Publication date: February 15, 2018
    Applicant: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Kuo-Kuang Yen, Yen-Chin Liao
  • Publication number: 20170302435
    Abstract: An encryption/decryption apparatus and a power analysis protecting method thereof are provided. The encryption/decryption apparatus adapted to perform encryption/decryption operation on digital data includes a data encryption/decryption unit, a random number generator, and a power analysis protecting circuit. The data encryption/decryption unit receives the digital data and performs an encryption/decryption operation on the digital data. The random number generator is used to generate random number data, the random number data has N bits, and N is a positive integer. The power analysis protecting circuit generates M kinds of power signals having different levels according to each bit data of the random number data when the random number data is received by the power analysis protecting circuit, and M is equal to the Nth power of 2.
    Type: Application
    Filed: March 13, 2017
    Publication date: October 19, 2017
    Applicant: Winbond Electronics Corp.
    Inventors: Chun-Yuan Yu, Szu-Chi Chung, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee
  • Publication number: 20170222757
    Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N?K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q?K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q?K frozen bits are allocated to the N?K frozen bit-channels and the q additional frozen bit-channels.
    Type: Application
    Filed: October 6, 2016
    Publication date: August 3, 2017
    Inventors: Yu-Ming HUANG, Hsiang-Pang LI, Hsie-Chia CHANG
  • Publication number: 20170111060
    Abstract: A method and a device for performing a polar codes channel-aware procedure are provided. A plurality of bit-channels have a polar code construction which is dynamic. The method includes the following steps. A plurality of reliability indices of some of the bit-channels are ranked. Whether an updating condition is satisfied is determined according to a ranking sequence of the reliability indices. If the updating condition is satisfied, the polar code construction is updated according to the ranking sequence of the reliability indices.
    Type: Application
    Filed: January 14, 2016
    Publication date: April 20, 2017
    Inventors: Yu-Ming Huang, Hsiang-Pang Li, Hsie-Chia Chang
  • Patent number: 9628114
    Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N?K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q?K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q?K frozen bits are allocated to the N?K frozen bit-channels and the q additional frozen bit-channels.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: April 18, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Ming Huang, Hsiang-Pang Li, Hsie-Chia Chang
  • Publication number: 20160294418
    Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N?K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q?K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q?K frozen bits are allocated to the N?K frozen bit-channels and the q additional frozen bit-channels.
    Type: Application
    Filed: July 8, 2015
    Publication date: October 6, 2016
    Inventors: Yu-Ming HUANG, Hsiang-Pang LI, Hsie-Chia CHANG
  • Patent number: 9460801
    Abstract: A method for determining a storing state of a flash memory is provided. The method includes the following steps. Firstly, plural first specific cell patterns are programmed into the flash memory. Then, plural second specific cell patterns are programmed into the flash memory. Then, a slicing voltage is adjusted to allow a distinguishable error percentage to be lower than a predetermined value. Afterwards, a first storing state and a second storing state of other cells of the flash memory are distinguished from each other according to the adjusted slicing voltage.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: October 4, 2016
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Chien-Fu Tseng, Hsie-Chia Chang, Yen-Yu Chou
  • Patent number: 9455724
    Abstract: A readout system includes a sensing module to generate first and second voltage signals with a phase difference associated with an environmental parameter, and a readout module configured to calibrate the phase difference, and to convert the calibrated phase difference into an output code.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: September 27, 2016
    Assignee: National Chiao Tung University
    Inventors: Kelvin Yi-Tse Lai, Zih-Cheng He, Yu-Tao Yang, Yu-Chi Kao, Hsie-Chia Chang, Chen-Yi Lee