Abstract: A method for realizing a finite field divider architecture is proposed, in which all standard basis of a divider are transformed into the composite field basis, and the circuit is realized using subfield multiplier, squarer, adder and lookup table over this composite field. The user can finish a division operation within one clock cycle and accomplish the requirement of low complexity. In many finite field operations, divider circuits like this are very helpful to RS/BCH decoders or ECC/Security processors.

Abstract: A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.

Abstract: A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.

Abstract: A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.

Abstract: The invention provides a method for updating check-node of low-density parity-check (LDPC) codes decoder. The method comprises the following steps: First of all, sort all data that are input into the check-node of LDPC codes decoder to find a minimum absolute value and a second minimum absolute value. Secondly, compare each of all the data to both of the minimum absolute value. If the compared data is equivalent to the current minimum absolute value, the compared data is updated by the secondary minimum absolute value. Otherwise, the compared data is updated by the minimum absolute value.

Abstract: The present invention discloses a method combining Trellis Coded Modulation (TCM) and Low-Density Parity Check (LDPC) code and the architecture thereof, which incorporates TCM with LDPC code having better error-correction capability to promote transmission quality and to define TCM of different transmission rates. Further, TCM can utilize less number of states to outperform the conventional spreading so that the hardware complexity in high-speed transmission can be reduced.

Abstract: A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.

Abstract: The present invention provides a method of calculating the syndrome polynomial in decoding error correction codes. From the relation between the syndromes and the coefficients of the error locator polynomial, the inference that the first t syndromes are zeros, then the next t syndromes are also zeros can be deduced, wherein t is the largest number of correctable errors. For all received codewords, the first t syndromes are calculated. Next, whether the first t syndromes are zeros is judged. If the first t syndromes are zeros, the computation is stopped; otherwise, the next t syndromes are calculated. Therefore, the present invention can judge whether the received codeword is erroneous with only a half of computation, hence effectively reducing the computation in practical operation and achieving the object of low power consumption.

Abstract: The present invention provides a method of calculating the syndrome polynomial in decoding error correction codes. From the relation between the syndromes and the coefficients of the error locator polynomial, the inference that the first t syndromes are zeros, then the next t syndromes are also zeros can be deduced, wherein t is the largest number of correctable errors. For all received codewords, the first t syndromes are calculated. Next, whether the first t syndromes are zeros is judged. If the first t syndromes are zeros, the computation is stopped; otherwise, the next t syndromes are calculated. Therefore, the present invention can judge whether the received codeword is erroneous with only a half of computation, hence effectively reducing the computation in practical operation and achieving the object of low power consumption.

Abstract: It is an object of the present invention to provide a method and apparatus for solving key equation polynomials in the decoding of codewords. Based upon the Euclidean algorithm, it can be implemented with minimal hardware circuitry and provide a method and apparatus for solving key equation within a t-step iterative decoding procedure while the prior art architectures require at most 2t iterations. It is yet another object of the present invention to provide a method and apparatus for solving key equation polynomials without decreasing the overall decoding speed of the decoder. Briefly, in a presently invention, a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step of the error correction code decoding process is presented whereby the polynomials are generated through at most t intermediate iterations that can be implemented with minimal amount of hardware circuitry.

Abstract: The presently invention discloses a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step of the error correction code decoding process whereby the polynomials are generated through at most t intermediate iterations that can be implemented with minimal amount of hardware circuitry. However, depending on the selected (N,K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of upstream data. Additionally, the present invention for computing the error locator polynomial and the error value polynomial employs an efficient scheduling of a small number of registers and finite-field multipliers (FFMs) without the need of finite-field inverters (FFIs) is illustrated. Using these new methods, a new area-efficient architecture that uses only 4t+2&rgr;+4 registers and three FFMs and no FFIs is presented to implement the inversionless Euclidean algorithm.

Abstract: In decoding an received codeword encoded for error correction purposes, a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step is presented whereby the polynomials are generated through a number of intermediate steps that can be implemented with minimal amount of hardware circuitry. The number of intermediate steps requires a corresponding number of cycles to complete the calculation of the polynomials. Depending on the selected (N, K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of up-stream data. More specifically, an efficient scheduling of a small number of finite-field multipliers (FFM's) without the need of finite-field inverters (FFI's) is disclosed. Using these new methods, an area-efficient architecture that uses only three FFM's and no FFI's is presented to implement a method derived from the inversionless Berlekamp-Massey algorithm.