Abstract: A conversion control circuit controls a power stage circuit of a switching power converter according to a first feedback signal and a second feedback signal, wherein the conversion control circuit includes an error amplifier circuit, a ramp signal generation circuit, a pulse width modulation circuit, and a quick response control circuit. The quick response control circuit performs a quick response control function, wherein the quick response control function includes: comparing the second feedback signal with at least one reference threshold to generate a quick response control signal; and when the second feedback signal crosses the reference threshold, adjusting a slope of a ramp signal according to the quick response control signal to accelerate an increase or decrease of the duty of a PWM signal, thereby accelerating the transient response of the switching power converter.

Abstract: A low dropout regulator having a current-limiting mechanism is disclosed. The regulator includes a sensing resistor, an error amplifier, and first through fourth transistors. The first transistor generates an output voltage according to an input voltage and a current control signal. The sensing resistor is employed to generate a sense voltage based on the current flowing through the fourth transistor so as to control the second transistor for generating an internal voltage. The third transistor controls the current control signal based on a voltage divided from the internal voltage. The channel width/length ratio of the first transistor is greater than that of the fourth transistor. When the third transistor is turned off, the error amplifier adjusts the voltage of the current control signal according to a voltage divided from the output voltage; when the third transistor is turned on, the voltage of the current control signal is not adjusted.

Abstract: A system for managing threads to handle transaction requests connected to input/output (I/O) subsystems to enable notification to threads to complete operations.

Abstract: A method for processing 2D operations in a tiled graphics architecture is disclosed. A graphics controller processes both 3D primitives and 2D blit operations. The 3D primitives are sorted into bins using well-known techniques. When a 2D blit operation is to be processed, the 2D blit operation is also sorted into bins. The sorted 3D primitives and sorted 2D blit operations are then delivered to blit and rendering engines on a bin-by-bin basis. By sorting the 2D blit operations into bins along with the 3D primitives, there is no need to flush the bins (send primitives to rendering engines) whenever a 2D blit operation requires processing. The sorting of 2D blit operations into bins reduces the frequency of graphics cache misses and improves graphics memory bandwidth utilization, thereby improving overall computer system performance.

Abstract: In a multiprocessor application server, multiple transaction types are determined. Performance statistics for each of the multiple transaction types are determined. The multiple transaction types are mapped to two or more processing units using the performance statistics to form a dispatch table. Incoming transactions are dispatched to the two or more processing units using the dispatch table.