Patents by Inventor Hsien-Chieh Lin

Hsien-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10798828
    Abstract: A method of fabricating a circuit board structure is provided. The method includes providing a core substrate; forming an insulation layer on the core substrate; forming a patterned metal layer on the insulation layer, wherein the patterned metal layer includes a wiring layer and a pad; forming a first metal pillar on the pad, wherein the first metal pillar has a top surface; and forming a first solder resist layer on the patterned metal layer and the first metal pillar, wherein the first solder resist layer has a first opening exposing the first metal pillar, and the first opening has a bottom surface, wherein the top surface of the metal pillar is higher than or equal to the bottom surface of the first opening.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 6, 2020
    Assignee: NAN YA PRINTED CIRCUIT BORED CORPORATION
    Inventor: Hsien-Chieh Lin
  • Publication number: 20200214145
    Abstract: A method of fabricating a circuit board structure is provided. The method includes providing a core substrate; forming an insulation layer on the core substrate; forming a patterned metal layer on the insulation layer, wherein the patterned metal layer includes a wiring layer and a pad; forming a first metal pillar on the pad, wherein the first metal pillar has a top surface; and forming a first solder resist layer on the patterned metal layer and the first metal pillar, wherein the first solder resist layer has a first opening exposing the first metal pillar, and the first opening has a bottom surface, wherein the top surface of the metal pillar is higher than or equal to the bottom surface of the first opening.
    Type: Application
    Filed: June 14, 2019
    Publication date: July 2, 2020
    Inventor: Hsien-Chieh LIN
  • Patent number: 10236395
    Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: March 19, 2019
    Assignees: Tatung Company, TATUNG UNIVERSITY
    Inventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
  • Publication number: 20160079449
    Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.
    Type: Application
    Filed: November 24, 2015
    Publication date: March 17, 2016
    Inventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
  • Patent number: 9224893
    Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 29, 2015
    Assignees: Tatung Company, TATUNG UNIVERSITY
    Inventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
  • Publication number: 20140159187
    Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.
    Type: Application
    Filed: February 7, 2013
    Publication date: June 12, 2014
    Applicants: TATUNG UNIVERSITY, TATUNG COMPANY
    Inventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
  • Patent number: 8420954
    Abstract: The invention provides a printed circuit board and a method for fabricating the same. The printed circuit board includes a core substrate having a first surface and an opposite second surface. A first through hole and a second through hole are formed through a portion of the core substrate, respectively from the first surface and second surfaces, wherein the first and second through holes are laminated vertically and connect to each other. A first guide rail and a second guide rail are, respectively, formed through a portion of the core substrate and connected to the second through hole, so that a fluid flows sequentially from an outside of the printed circuit board through the first guide rail, the second through hole and the second guide rail, to the outside of the printed circuit board.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 16, 2013
    Assignee: Nan Ya PCB Corp.
    Inventors: Hsien-Chieh Lin, Tung-Yu Chang
  • Patent number: 8378225
    Abstract: The invention provides a printed circuit board and method for fabricating the same. The printed circuit board includes a substrate having an internal circuit structure. An additional circuit structure is disposed on the substrate, electrically connected to the internal circuit structure. A solder mask insulating layer having an opening is disposed on the additional circuit structure. A conductive bump pattern is disposed in the solder mask insulating layer, wherein the conductive bump pattern extends into the opening horizontally, wherein a side, a portion of an upper surface and a portion of a lower surface of the conductive bump pattern are exposed from the opening. A solder ball is formed in the opening, wherein the solder ball is electrically connected to the additional circuit structure.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: February 19, 2013
    Assignee: Nan Ya PCB Corp.
    Inventor: Hsien-Chieh Lin
  • Patent number: 8243464
    Abstract: Disclosed is a printed circuit board structure which is manufactured by providing a core board, forming an inner circuit layer on the core board surface, forming a bonding pad on the inner circuit, forming a ring-shaped anti-etching layer on the bonding pad, forming an anti-soldering insulation layer on the ring-shaped anti-etching layer and the bonding pad, and forming an opening to expose a part of the bonding pad, wherein the radius of the opening is shorter than the radius of the ring-shaped anti-etching layer, and the bonding pad surface is free of concave. The described structure may prevent the solder extending along the bottom void of the anti-soldering insulation layer to other regions.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 14, 2012
    Assignee: Nan Ya PCB Corp.
    Inventor: Hsien-Chieh Lin
  • Publication number: 20120043127
    Abstract: The invention provides a printed circuit board and a method for fabricating the same. The printed circuit board includes a core substrate having a first surface and an opposite second surface. A first through hole and a second through hole are formed through a portion of the core substrate, respectively from the first surface and second surfaces, wherein the first and second through holes are laminated vertically and connect to each other. A first guide rail and a second guide rail are, respectively, formed through a portion of the core substrate and connected to the second through hole, so that a fluid flows sequentially from an outside of the printed circuit board through the first guide rail, the second through hole and the second guide rail, to the outside of the printed circuit board.
    Type: Application
    Filed: November 30, 2010
    Publication date: February 23, 2012
    Applicant: NAN YA PCB CORP.
    Inventors: Hsien-Chieh LIN, Tung-Yu Chang
  • Publication number: 20110220403
    Abstract: The invention provides a side packaged type printed circuit board. The side packaged type printed circuit board includes a circuit substrate having a surface and an adjacent side surface. An inner circuit covers a portion of the surface. A first side electrical connecting pad electrically connects to the inner circuit, wherein the first side electrical connecting pad and the inner circuit are in the same additional layer.
    Type: Application
    Filed: April 16, 2010
    Publication date: September 15, 2011
    Applicant: NAN YA PCB CORP.
    Inventor: Hsien-Chieh Lin
  • Publication number: 20110100695
    Abstract: Disclosed is a printed circuit board structure which is manufactured by providing a core board, forming an inner circuit layer on the core board surface, forming a bonding pad on the inner circuit, forming a ring-shaped anti-etching layer on the bonding pad, forming an anti-soldering insulation layer on the ring-shaped anti-etching layer and the bonding pad, and forming an opening to expose a part of the bonding pad, wherein the radius of the opening is shorter than the radius of the ring-shaped anti-etching layer, and the bonding pad surface is free of concave. The described structure may prevent the solder extending along the bottom void of the anti-soldering insulation layer to other regions.
    Type: Application
    Filed: December 23, 2009
    Publication date: May 5, 2011
    Applicant: NAN YA PCB CORP.
    Inventor: Hsien-Chieh Lin
  • Publication number: 20110036620
    Abstract: The invention provides a printed circuit board and method for fabricating the same. The printed circuit board includes a substrate having an internal circuit structure. An additional circuit structure is disposed on the substrate, electrically connected to the internal circuit structure. A solder mask insulating layer having an opening is disposed on the additional circuit structure. A conductive bump pattern is disposed in the solder mask insulating layer, wherein the conductive bump pattern extends into the opening horizontally, wherein a side, a portion of an upper surface and a portion of a lower surface of the conductive bump pattern are exposed from the opening from the opening. A solder ball is formed in the opening, wherein the solder ball is electrically connected to the additional circuit structure.
    Type: Application
    Filed: September 21, 2009
    Publication date: February 17, 2011
    Applicant: NAN YA PCB CORP.
    Inventor: Hsien-Chieh Lin
  • Patent number: 7576287
    Abstract: A lot traceable printed circuit board (PCB) includes a substrate having thereon a patterned circuit layer and a working zone carrying production information related to the PCB itself. The working zone includes a plurality of code boxes, wherein each of the code boxes has a first probe region and second probe region. A single set of resistance test loop is disposed within the first probe region. Four sets of resistance test loops are disposed within the second probe region. A frying probe tester is used to probe the set of resistance test loops respectively for abstracting the production information recorded in the working zone.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: August 18, 2009
    Assignee: Nan Ya Printed Circuit Board Corporation
    Inventors: Hsing-Lun Lo, Hsien-Chieh Lin, Kuo-Chun Chiang, Shing-Fun Ho
  • Patent number: 7528482
    Abstract: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: May 5, 2009
    Assignee: Nan Ya Printed Circuit Board Corporation
    Inventors: Cheng-Hung Huang, Hsien-Chieh Lin, Kuo-Chun Chiang, Shing-Fun Ho
  • Patent number: 7521800
    Abstract: A solder pad structure includes a first metal layer disposed on an insulation layer, wherein the first metal layer is electrically connected with an underlying interconnection circuit layer through a conductive through hole disposed in the insulation layer. A solder resist layer having an opening exposing a central portion of the first metal layer is disposed on the insulating layer. A pillar-shaped second metal layer is disposed within the opening directly on the first metal layer. A solder ball filled into the opening is in contact with the pillar-shaped second metal layer.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: April 21, 2009
    Assignee: Nan Ya Printed Circuit Board Corporation
    Inventors: Chih-Chung Chu, Shih-Tsung Lin, Hsien-Chieh Lin
  • Publication number: 20080315398
    Abstract: An embedded chip package includes a substrate having a dielectric interposer, a first metal foil on a first surface and a second metal foil on a second surface of the substrate, wherein the substrate has a cavity recessed into the first surface; a metal heatsink embedded within the cavity; a semiconductor die mounted on a flat bottom of the metal heatsink; a dielectric layer covering the first surface of the substrate; at least one built-up circuit trace layer on the dielectric layer; a solder resist layer on the built-up circuit trace layer and on the dielectric layer; a heat-dissipating metal layer on the second metal foil; and heat-dissipating plugs connecting the flat bottom of the metal heatsink and the heat-dissipating metal layer.
    Type: Application
    Filed: July 30, 2007
    Publication date: December 25, 2008
    Inventors: Hsing-Lun Lo, Shih-Tsung Lin, Hsien-Chieh Lin, Kuo-Chun Chiang
  • Publication number: 20080251917
    Abstract: A solder pad structure includes a first metal layer disposed on an insulation layer, wherein the first metal layer is electrically connected with an underlying interconnection circuit layer through a conductive through hole disposed in the insulation layer. A solder resist layer having an opening exposing a central portion of the first metal layer is disposed on the insulating layer. A pillar-shaped second metal layer is disposed within the opening directly on the first metal layer. A solder ball filled into the opening is in contact with the pillar-shaped second metal layer.
    Type: Application
    Filed: May 24, 2007
    Publication date: October 16, 2008
    Inventors: Chih-Chung Chu, Shih-Tsung Lin, Hsien-Chieh Lin
  • Publication number: 20080149732
    Abstract: A lot traceable printed circuit board (PCB) includes a substrate having thereon a patterned circuit layer and a working zone carrying production information related to the PCB itself. The working zone includes a plurality of code boxes, wherein each of the code boxes has a first probe region and second probe region. A single set of resistance test loop is disposed within the first probe region. Four sets of resistance test loops are disposed within the second probe region. A frying probe tester is used to probe the set of resistance test loops respectively for abstracting the production information recorded in the working zone.
    Type: Application
    Filed: February 12, 2007
    Publication date: June 26, 2008
    Inventors: Hsing-Lun Lo, Hsien-Chieh Lin, Kuo-Chun Chiang, Shing-Fun Ho
  • Publication number: 20080116569
    Abstract: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.
    Type: Application
    Filed: February 7, 2007
    Publication date: May 22, 2008
    Inventors: Cheng-Hung Huang, Hsien-Chieh Lin, Kuo-Chun Chiang, Shing-Fun Ho