Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A method for repairing a polishing pad in real time includes a trimming step, a detection step, and a reconstruction and analysis step. A surface morphology of the polishing pad is reconstructed through detection, and analysis is performed according to the reconstruction, to ensure that a surface of the polishing pad can recover its function after the surface of the polishing pad is trimmed, so that the polishing pad can be used effectively to reduce costs.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: Provided is a dressing device for a carrier. The dressing device comprises a dresser, a swing arm, a base and at least one damper. A first end and a second end of the swing arm are coupled to the dresser and the base, respectively, and the at least one damper is disposed inside the swing arm. Any axial vibration of the dresser or the swing arm during dressing for the carrier can be compensated or attenuated by the damper in an active manner properly, so as to make the surface of the carrier flatter and more uniform, which not only improves a removal rate of material and a polishing result of the surface in the subsequent chemical mechanical planarization process, but also prolongs the service life of the carrier. The present disclosure further relates to a polishing system for dressing the carrier by using the said dressing device.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: Disclosed are a detection method and a detection apparatus for a polishing pad of a chemical mechanical polishing device, particularly a detection method and a detection apparatus for detecting a surface of a polishing pad dynamically. An isolation region isolated by a gas to expose the polishing pad is formed by the detecting device, and a detection is performed on the isolation region, such that the chemical mechanical polishing device is capable of detecting the polishing pad without interrupting a manufacturing process and the detection results with more accurate can be achieved. Thereby, the polishing pad can be repaired and replaced more timely.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.

Abstract: A system and a method for uniformed surface measurement are provided, in which a sensor is provided to perform measurements on a carrier in a polishing machine, and a measuring trajectory of the sensor on the carrier is adjusted by controlling the pivoting of a sensor carrier carrying the sensor and the rotation of a rotating platform in the polishing machine in order to achieve uniformed surface measurements of the carrier and real-time constructions of the surface topography. This allows the polishing state of the carrier to be monitored in real time, thereby improving the efficiency of the polishing process. A sensing apparatus for uniformed surface measurement is also provided.

Abstract: Disclosed herein are novel synthetic polypeptides and uses thereof in the preparation of liposomes. According to embodiments of the present disclosure, the synthetic polypeptide comprises a membrane lytic motif, a masking motif, and a linker configured to link the membrane lytic motif and the masking motif. The linker is cleavable by a stimulus, such as, light, protease, or phosphatase. Once being coupled to a liposome, the exposure to the stimulus cleaves the linker that results in the separation of the masking motif from the membrane lytic motif, which in turn exerts membrane lytic activity on the liposome that leads to the collapse of the intact structure of the liposome, and releases the agent encapsulated in the liposome to the target site. Also disclosed herein are methods of diagnosing or treating a disease in a subject by use of the present liposomes.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: Disclosed herein are novel synthetic polypeptides and uses thereof in the preparation of liposomes. According to embodiments of the present disclosure, the synthetic polypeptide comprises a membrane lytic motif, a masking motif, and a linker configured to link the membrane lytic motif and the masking motif. The linker is cleavable by a stimulus, such as, light, protease, or phosphatase. Once being coupled to a liposome, the exposure to the stimulus cleaves the linker that results in the separation of the masking motif from the membrane lytic motif, which in turn exerts membrane lytic activity on the liposome that leads to the collapse of the intact structure of the liposome, and releases the agent encapsulated in the liposome to the target site. Also disclosed herein are methods of diagnosing or treating a disease in a subject by use of the present liposomes.