Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: A method for repairing a polishing pad in real time includes a trimming step, a detection step, and a reconstruction and analysis step. A surface morphology of the polishing pad is reconstructed through detection, and analysis is performed according to the reconstruction, to ensure that a surface of the polishing pad can recover its function after the surface of the polishing pad is trimmed, so that the polishing pad can be used effectively to reduce costs.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer.

Abstract: Provided is a semiconductor device including a fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer is disposed over the second layer. The second layer includes a base material and a dopant doped in the base material. The dopant comprises Al, Ta, W, or a combination thereof. The first layer and the second layer comprise different materials. A method of manufacturing the semiconductor device is also provided.

Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and a filter layer, and strain layers. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. The gate stack includes a gate dielectric layer, a work function layer and a metal filling layer. The gate dielectric layer is disposed on the semiconductor fin. The work function layer is disposed on the gate dielectric layer. The metal filling layer is over the work function layer. The filter layer is disposed between the work function layer and the metal filling layer to prevent or decrease penetration of diffusion atoms. The strain layers are beside the gate stack. A material of the filter layer is different from a material of the work function layer and a material of the metal filling layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A clamping fixture includes a body, a connector, a first clasp, at least one first elastic member and a lock. The connector is movable relative to the body along a first direction. The first clasp includes a first fastener and is disposed at one end of the connector. The at least one first elastic member is configured to apply force to the body and the connector along the first direction. The lock includes a second fastener. The first clasp and the lock are coupled through the first fastener and the second fastener.

Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: Disclosed herein are novel synthetic polypeptides and uses thereof in the preparation of liposomes. According to embodiments of the present disclosure, the synthetic polypeptide comprises a membrane lytic motif, a masking motif, and a linker configured to link the membrane lytic motif and the masking motif. The linker is cleavable by a stimulus, such as, light, protease, or phosphatase. Once being coupled to a liposome, the exposure to the stimulus cleaves the linker that results in the separation of the masking motif from the membrane lytic motif, which in turn exerts membrane lytic activity on the liposome that leads to the collapse of the intact structure of the liposome, and releases the agent encapsulated in the liposome to the target site. Also disclosed herein are methods of diagnosing or treating a disease in a subject by use of the present liposomes.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.

Abstract: A clamping fixture includes a body, a connector, a first clasp, at least one first elastic member and a lock. The connector is movable relative to the body along a first direction. The first clasp includes a first fastener and is disposed at one end of the connector. The at least one first elastic member is configured to apply force to the body and the connector along the first direction. The lock includes a second fastener. The first clasp and the lock are coupled through the first fastener and the second fastener.