Patents by Inventor Hsien-Yen Chiu

Hsien-Yen Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190230799
    Abstract: A power supply with a staggered configuration includes a housing having an accommodation space, a first power supply module, a second power supply module, and an electric fan which are disposed inside the accommodation space. The first power supply module includes a first frontend power conversion unit and a first backend power conversion unit which are disposed at separate airflow passages. When the power supply is in operation, the electric fan turns and drives the air to flow into the housing in such a way that one airflow passage is through the first frontend power conversion unit and another airflow passage is through the first backend power conversion unit. In this way, the heat dissipation efficiency is increased with two separated air flow passages respectively flowing through and cooling down the first frontend power conversion unit and the first backend power conversion unit.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Inventors: Jui Yang CHIU, Cheng-Yen YEH, Hsien-Te CHIU
  • Patent number: 10342144
    Abstract: A power supply with a staggered configuration includes a housing having an accommodation space, a first power supply module, a second power supply module, and an electric fan which are disposed inside the accommodation space. The first power supply module includes a first frontend power conversion unit and a first backend power conversion unit which are disposed at separate airflow passages. When the power supply is in operation, the electric fan turns and drives the air to flow into the housing in such a way that one airflow passage is through the first frontend power conversion unit and another airflow passage is through the first backend power conversion unit. In this way, the heat dissipation efficiency is increased with two separated air flow passages respectively flowing through and cooling down the first frontend power conversion unit and the first backend power conversion unit.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 2, 2019
    Assignee: ACBEL POLYTECH INC.
    Inventors: Jui Yang Chiu, Cheng-Yen Yeh, Hsien-Te Chiu
  • Patent number: 8005660
    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: August 23, 2011
    Assignee: Anova Solutions, Inc.
    Inventors: Hsien-Yen Chiu, Meiling Wang, Jun Li
  • Patent number: 7549134
    Abstract: Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ratio of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 16, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jun Li, Athanasius Spyrou, Hong Zhao, Hsien-Yen Chiu
  • Publication number: 20080059143
    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.
    Type: Application
    Filed: June 27, 2007
    Publication date: March 6, 2008
    Inventors: Hsien-Yen Chiu, Meiling Wang, Jun Li
  • Patent number: 7243320
    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces a large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance memos to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: July 10, 2007
    Assignee: Anova Solutions, Inc.
    Inventors: Hsien-Yen Chiu, Meiling Wang, Jun Li
  • Publication number: 20060150129
    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.
    Type: Application
    Filed: December 12, 2005
    Publication date: July 6, 2006
    Inventors: Hsien-Yen Chiu, Meiling Wang, Jun Li
  • Patent number: 7073140
    Abstract: Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ration of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: July 4, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jun Li, Athanasius Spyrou, Hong Zhao, Hsien-Yen Chiu
  • Patent number: 6721929
    Abstract: A variable current source model accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive (“RC”) network. The RC network couples a driving point and a receiving point, and a circuit specified in the design, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization model of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: April 13, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jun Li, Hong Zhao, Hsien-Yen Chiu
  • Publication number: 20020021135
    Abstract: A variable current source model accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive (“RC”) network. The RC network couples a driving point and a receiving point, and a circuit specified in the design, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization model of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point.
    Type: Application
    Filed: May 11, 2001
    Publication date: February 21, 2002
    Inventors: Jun Li, Hong Zhao, Hsien-Yen Chiu