Patents by Inventor Hsih-Yang Chiu

Hsih-Yang Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035918
    Abstract: A semiconductor structure includes a semiconductor substrate, a shielding structure, a ground terminal, and a through silicon via. The shielding structure is disposed over the semiconductor substrate and includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer is disposed over the semiconductor substrate. The second metal layer is disposed over the first metal layer. The third metal layer is disposed over the second metal layer. The ground terminal is electrically connected to the third metal layer. The through silicon via is disposed over the semiconductor substrate and adjacent to the shielding structure.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Ting-Cih KANG, Hsih-Yang CHIU
  • Patent number: 10910345
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The second die is stacked on the first die, the first redistribution layer is disposed between a first substrate of the first die and a second ILD layer of the second die, and the second redistribution layer is disposed on a second substrate of the second die. The first interconnect structure connects the first redistribution layer to one of first metal lines of the first die, and the second interconnect structure connects the second redistribution layer to one of the second metal lines in the second ILD layer.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: February 2, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Pei-Jhen Wu, Ching-Hung Chang, Hsih-Yang Chiu
  • Publication number: 20210020590
    Abstract: The present disclosure relates to an electronic device with an integral filtering component. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Inventors: HSIH-YANG CHIU, TING-CIH KANG
  • Patent number: 10896848
    Abstract: A method of manufacturing a semiconductor device includes forming a precursor structure including a substrate having a via hole, a liner on a sidewall of the via hole, a conductor in the via hole, a first and a second insulating layers respectively on the top and bottom surfaces, and a first and a second redistribution layers in contact with the conductor through a first hole in the first insulating layer and a second hole in the second insulating layer. A first opening and a second opening are then respectively formed in the first insulating layer and the second insulating layer to expose a portion of the liner. The liner is then etched through the first opening and the second opening to form an air gap surrounding the conductor. The first opening and the second opening are then filled to seal the air gap.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: January 19, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10886236
    Abstract: An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: January 5, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Cih Kang, Hsih-Yang Chiu
  • Publication number: 20200402956
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes steps of providing semiconductor wafer having a plurality of device chips disposed thereon, wherein each of the plurality of device chips has an active area and an inactive area arranged around the active area; forming a plurality of the openings, wherein each of the plurality of openings is formed in a back surface of the semiconductor wafer and forms an opening into the inactive area; and disposing a protecting material within the openings and over the back surface of the semiconductor wafer.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventor: Hsih-Yang Chiu
  • Patent number: 10861711
    Abstract: A method of manufacturing a semiconductor structure includes forming a precursor structure including a plurality of conductive pads on a substrate, an etch stop layer between the conductive pads, and an UBM layer on the conductive pads and the etch stop layer. A plurality of mask structures are formed on the UBM layer, and a plurality of openings are formed between thereof. Each of the mask structures is located on one of the conductive pads, and the openings expose a first portion of the UBM layer. A supporting layer is formed in the openings. The mask structures are removed to form a plurality of cavities exposing a second portion of the UBM layer. A conductive material layer is formed in the cavities. The supporting layer is removed. The first portion of the UBM layer is removed to form a plurality of conductive bumps separated from each other.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: December 8, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Publication number: 20200357765
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: PEI-JHEN WU, HSIH-YANG CHIU, CHIANG-LIN SHIH, CHING-HUNG CHANG, YI-JEN LO
  • Patent number: 10833029
    Abstract: The present disclosure relates to an electronic device and a method of manufacturing a filtering component of the electronic device. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 10, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Hsih-Yang Chiu, Ting-Cih Kang
  • Publication number: 20200350284
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The second die is stacked on the first die, the first redistribution layer is disposed between a first substrate of the first die and a second ILD layer of the second die, and the second redistribution layer is disposed on a second substrate of the second die. The first interconnect structure connects the first redistribution layer to one of first metal lines of the first die, and the second interconnect structure connects the second redistribution layer to one of the second metal lines in the second ILD layer.
    Type: Application
    Filed: May 2, 2019
    Publication date: November 5, 2020
    Inventors: CHIANG-LIN SHIH, PEI-JHEN WU, CHING-HUNG CHANG, HSIH-YANG CHIU
  • Patent number: 10825796
    Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a device chip and a protecting material. The device chip has an active area and an inactive area arranged around the active area. The protecting material includes a first portion and a second portion, the first portion is disposed within the inactive area and encircles the active area, and the second portion is disposed over a lower surface of the device chip.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 3, 2020
    Assignee: Nanya Technology Corporation
    Inventor: Hsih-Yang Chiu
  • Patent number: 10818541
    Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a semiconductor substrate, an air gap region, a capping layer, and an isolating layer. The air gap region is disposed in the semiconductor substrate. The capping layer is disposed on the air gap region. The isolating layer is disposed on the semiconductor substrate and partially encircles the capping layer.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 27, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10811382
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 20, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Pei-Jhen Wu, Hsih-Yang Chiu, Chiang-Lin Shih, Ching-Hung Chang, Yi-Jen Lo
  • Patent number: 10803966
    Abstract: A method of blowing an antifuse element is disclosed. An antifuse element including a first conductor, a second conductor, and a dielectric layer disposed between the first conductor and the second conductor is received, wherein the dielectric layer has a breakdown voltage. A first voltage is applied between the first conductor and the second conductor within a first time period, wherein the first voltage is less than the breakdown voltage. After applying the first voltage, a second voltage is applied between the first conductor and the second conductor to blow the antifuse element within a second time period, wherein the second voltage is greater than the breakdown voltage.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 13, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10804184
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a restraint layer, a plurality of contact plugs, and a plurality of through silicon vias. The restraint layer is disposed on the semiconductor substrate, and the contact plugs are inserted into the restraint layer. The through silicon vias extend from a bottom surface of the semiconductor substrate to a front surface opposite to the back surface and the through silicon vias are in contact with the contact plugs, respectively.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 13, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10734338
    Abstract: The present disclosure relates to a multi-ring bonding pad, a semiconductor structure having the multi-ring bonding pad, and a method of manufacturing the semiconductor structure. The bonding pad includes an inner ring member, an outer ring member, and multiple bridge members. The inner ring member has a pair of first inner edges opposite to each other, a pair of second inner edges opposite to each other, and multiple third inner edges for connecting the first inner edges to the second inner edges. The outer ring member surrounds the inner ring member and has a pair of first outer edges opposite to each other, a pair of second outer edges opposite to each other, and multiple third outer edges for connecting the first outer edges to the second outer edges. The bridge members are disposed between the inner ring member and the outer ring member for connecting the inner ring member to the outer ring member.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: August 4, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Pei-Jhen Wu, Chiang-Lin Shih, Hsih-Yang Chiu
  • Patent number: 10734308
    Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate and at least one through silicon via. The through silicon via includes a conductive plug, a first insulation layer, and a diffusion barrier layer. The conductive plug penetrates through the semiconductor substrate. The first insulation layer surrounds the conductive plug. The diffusion barrier layer is disposed between the conductive plug and the first insulation layer, and is utilized to prevent out-diffusion of dopant impurities from the conductive plug to the semiconductor substrate.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 4, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Publication number: 20200211893
    Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a semiconductor substrate, an air gap region, a capping layer, and an isolating layer. The air gap region is disposed in the semiconductor substrate. The capping layer is disposed on the air gap region. The isolating layer is disposed on the semiconductor substrate and partially encircles the capping layer.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 2, 2020
    Inventor: HSIH-YANG CHIU
  • Publication number: 20200176358
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a restraint layer, a plurality of contact plugs, and a plurality of through silicon vias. The restraint layer is disposed on the semiconductor substrate, and the contact plugs are inserted into the restraint layer. The through silicon vias extend from a bottom surface of the semiconductor substrate to a front surface opposite to the back surface and the through silicon vias are in contact with the contact plugs, respectively.
    Type: Application
    Filed: February 21, 2019
    Publication date: June 4, 2020
    Inventor: Hsih-Yang CHIU
  • Publication number: 20200176403
    Abstract: The present disclosure relates to an electronic device and a method of manufacturing a filtering component of the electronic device. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 4, 2020
    Inventors: Hsih-Yang CHIU, Ting-Cih KANG