Patents by Inventor Hsin-Chang Lee

Hsin-Chang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11029593
    Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
  • Patent number: 11022874
    Abstract: The present disclosure provides a mask. The mask includes a substrate; an etch stop layer disposed on the substrate, wherein the etch stop layer includes at least one of ruthenium oxide, tungsten nitride, and titanium nitride and is doped with at least one of phosphorous (P), calcium (Ca), and sodium (Na); and a material layer disposed on the etch stop layer and patterned to have an opening, wherein the etch stop layer completely covers a portion of the substrate within the opening.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee
  • Patent number: 11005007
    Abstract: The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprising: a light-emitting stack; and a semiconductor layer having a first surface connecting to the light-emitting stack, a second surface opposite to the first surface, and a void; wherein the void comprises a bottom part near the first surface and an opening on the second surface, and a dimension of the bottom part is larger than the dimension of the opening.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 11, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Wen-Luh Liao, Chih-Chiang Lu, Shih-Chang Lee, Hung-Ta Cheng, Hsin-Chan Chung, Yi-Chieh Lin
  • Patent number: 10996553
    Abstract: A reticle and a method for manufacturing the same are provided. The reticle includes a mask substrate, a reflective multilayer (ML), a capping layer and an absorption composite structure. The reflective ML is positioned over a front-side surface of the mask substrate. The capping layer is positioned over the reflective ML. The absorption composite structure is positioned over the capping layer. The absorption composite structure includes a first absorption layer, a second absorption layer, a third absorption layer and an etch stop layer. The first absorption layer is positioned over the capping layer. The second absorption layer is positioned over the first absorption layer. The third absorption layer is positioned over the second absorption layer. The etch stop layer is positioned between the first absorption layer and the second absorption layer. The first absorption layer and the second absorption layer are made of the same material.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chang Hsueh, Huan-Ling Lee, Chia-Jen Chen, Hsin-Chang Lee
  • Publication number: 20210072633
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Ching-Huang CHEN, Chi-Yuan SUN, Hua-Tai LIN, Hsin-Chang LEE, Ming-Wei CHEN
  • Publication number: 20210055646
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Publication number: 20210033960
    Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.
    Type: Application
    Filed: January 29, 2020
    Publication date: February 4, 2021
    Inventors: Pei-Cheng Hsu, Chun-Fu Yang, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 10871721
    Abstract: A mask for cleaning a lithography apparatus includes a mask substrate and a coating provided on a surface of the mask substrate. The coating is configured to trap particulate contaminant matter from the lithography apparatus. A method of cleaning a lithography tool is also provided preparing a cleaning mask including a particle trapping layer formed on a substrate. The method includes transferring the cleaning mask through a mask transferring route of the lithography tool. Subsequently, the method includes analyzing a particle trapped by the particle trapping layer.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Wei Chen, Hsin-Chang Lee, Ping-Hsun Lin
  • Patent number: 10866504
    Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
  • Patent number: 10859906
    Abstract: The present disclosure describes a method to form alignment marks on or in the top layer of an extreme ultraviolet (EUV) mask blank without the use of photolithographic methods. For example, the method can include forming a metal structure on the top layer of the EUV mask blank by dispensing a hexacarbonylchromium vapor on the top layer of the EUV mask and exposing the hexacarbonylchromium vapor to an electron-beam. The hexacarbonylchromium vapor is decomposed to form the metal structure at an area which is proximate to where the hexacarbonylchromium vapors interact with the electron-beam. In another example, the method can include forming a patterned structure in the top layer of an EUV mask blank with the use of an etcher aperture and an etching process.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yi-Fu Hsieh, Chih-Chiang Tu, Jong-Yuh Chang, Hsin-Chang Lee
  • Patent number: 10816892
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-CHeng Ho, Chen-Shao Hsu
  • Publication number: 20200264505
    Abstract: A pellicle includes a frame. The frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle; and a bottom surface of the frame defines only a single recess therein. The pellicle further includes a gasket configured to fit within the single recess.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Chue San YOO, Hsin-Chang LEE, Pei-Cheng HSU, Yun-Yue LIN
  • Patent number: 10747103
    Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Yue Lin, Hsuan-Chen Chen, Chih-Cheng Lin, Hsin-Chang Lee, Yao-Ching Ku, Wei-Jen Lo, Anthony Yen, Chin-Hsiang Lin, Mark Chien
  • Patent number: 10670959
    Abstract: A pellicle includes a frame. The frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle. The frame further includes a recess in a bottom surface of the frame. The pellicle further includes a membrane extending across the frame. The pellicle further includes a gasket configured to fit within the recess.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chue San Yoo, Hsin-Chang Lee, Pei-Cheng Hsu, Yun-Yue Lin
  • Publication number: 20200150527
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a porous pellicle frame, a mask with a patterned surface, a first thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame, and a second thermal conductive adhesive layer that secures the porous pellicle frame to the mask.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: AMO CHEN, YUN-YUE LIN, TA-CHENG LIEN, HSIN-CHANG LEE, CHIH-CHENG LIN, JENG-HORNG CHEN
  • Publication number: 20200124958
    Abstract: A method of performing a lithography process includes receiving a lithography mask and performing overlay measurement. The lithography mask includes a substrate that contains a low thermal expansion material (LTEM); a reflective structure over a first side of the substrate; an absorber layer over the reflective structure and containing one or more first overlay marks; and a conductive layer over a second side of the substrate and containing one or more second overlay marks. The second side is opposite the first side. The overlay measurement includes using the one or more first overlay marks in an extreme ultraviolet (EUV) lithography process or using the one or more second overlay marks in a non-EUV lithography process.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Chih-Cheng Lin, Anthony Yen, Chin-Hsiang Lin
  • Publication number: 20200103745
    Abstract: A method includes placing a photomask having a contamination on a surface thereof in a plasma processing chamber. The contaminated photomask is plasma processed in the plasma processing chamber to remove the contamination from the surface. The plasma includes oxygen plasma or hydrogen plasma.
    Type: Application
    Filed: September 11, 2019
    Publication date: April 2, 2020
    Inventors: Chun-Fu YANG, Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
  • Publication number: 20200103769
    Abstract: A mask for cleaning a lithography apparatus includes a mask substrate and a coating provided on a surface of the mask substrate. The coating is configured to trap particulate contaminant matter from the lithography apparatus. A method of cleaning a lithography tool is also provided preparing a cleaning mask including a particle trapping layer formed on a substrate. The method includes transferring the cleaning mask through a mask transferring route of the lithography tool. Subsequently, the method includes analyzing a particle trapped by the particle trapping layer.
    Type: Application
    Filed: September 17, 2019
    Publication date: April 2, 2020
    Inventors: Ming-Wei CHEN, Hsin-Chang LEE, Ping-Hsun LIN
  • Publication number: 20200103742
    Abstract: In a method of manufacturing a photo mask, an etching mask layer having circuit patterns is formed over a target layer of the photo mask to be etched. The photo mask includes a backside conductive layer. The target layer is etched by plasma etching, while preventing active species of plasma from attacking the backside conductive layer.
    Type: Application
    Filed: April 12, 2019
    Publication date: April 2, 2020
    Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Ta-Cheng LIEN, Tzu Yi WANG
  • Publication number: 20200103743
    Abstract: A photo mask for extreme ultra violet (EUV) lithography includes a substrate having a front surface and a back surface opposite to the front surface, a multilayer Mo/Si stack disposed on the front surface of the substrate, a capping layer disposed on the multilayer Mo/Si stack, an absorber layer disposed on the capping layer, and a backside conductive layer disposed on the back surface of the substrate. The backside conductive layer is made of tantalum boride.
    Type: Application
    Filed: April 12, 2019
    Publication date: April 2, 2020
    Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Ping-Hsun LIN, Ta-Cheng LIEN, Tzu Yi WANG