Patents by Inventor Hsin-Che Chiang

Hsin-Che Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098312
    Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first fin structure with a first composition and a second fin structure with a second composition, oxidizing the first fin structure to form a first oxide layer and oxidizing the second fin structure to form a second oxide layer, removing the second oxide layer formed on the second fin structure, oxidizing the second fin structure to form a third oxide layer over the second fin structure, and forming a first metal gate electrode layer over the first oxide layer and a second metal gate electrode layer over the third oxide layer.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Hsin-Che CHIANG, Yu-San CHIEN, Ta-Chun LIN, Chun-Sheng LIANG, Kuo-Hua PAN
  • Publication number: 20210082686
    Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Kuo-Hua Pan
  • Publication number: 20210066476
    Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.
    Type: Application
    Filed: July 10, 2020
    Publication date: March 4, 2021
    Inventors: Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang, Kuo-Hua Pan
  • Publication number: 20210043564
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Yi-Che Chiang
  • Patent number: 10912948
    Abstract: The present invention provides a composite intelligent biological phototherapy device including a base structure, a plurality of white light fluorescent tubes arranged side by side on the base structure, a plurality of LEDs disposed between the white light fluorescent tubes, a housing having an opening and configured to accommodate the base structure and the white light fluorescent tubes and the LEDs thereon, a light-transmittable plate disposed on the housing corresponding to the opening, and an control module configured to respectively control the white light fluorescent tubes and the LEDs. The base structure includes a plurality of sections, and each of the sections has a first surface facing the light-transmittable plate. The white light fluorescent tubes and the LEDs are provided on the first surfaces, and the sections are bent relative to each other so an angle between the first surfaces of adjacent sections is less than 180 degrees.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 9, 2021
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Yi-Cheng Lin, Hsin-Yi Tsai, Min-Wei Hung, Kuo-Cheng Huang, Hsin-Su Yu, Chiou-Lian Lai, Chung-Yao Hsu, Chao-Hung Cheng, Li-Wei Kuo, Hung-Che Chiang, Chih-Yi Yang
  • Patent number: 10879393
    Abstract: A method of fabricating a semiconductor device includes forming a dummy gate structure on a substrate, forming gate spacers on sidewalls of the dummy gate structure, and depositing an interlayer dielectric layer around the gate spacers. The method also includes removing the dummy gate structure to form a space between the gate spacers, and forming a gate structure in the space, wherein the gate structure includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer. The method further includes removing a portion of the gate electrode layer to form a recess that is surrounded by the gate dielectric layer. In addition, the method includes implanting on the interlayer dielectric layer to form a strained layer for bending the gate dielectric layer and the gate spacers towards the recess.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Jeng-Ya Yeh
  • Patent number: 10867806
    Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Kuo-Hua Pan
  • Publication number: 20200388526
    Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Hsin-Che Chiang, Ju-Li Huang, Chun-Sheng Liang, Jeng-Ya Yeh
  • Patent number: 10854506
    Abstract: A semiconductor device includes a substrate, a gate stack over the substrate, an insulating structure over the gate stack, a conductive via in the insulating structure, and an contact etch stop layer (CESL) over the insulating structure. The insulating structure has an air slit therein. The conductive via is electrically connected to the gate stack. A portion of the CESL is exposed in the air slit.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Sheng Liang, Wei-Chih Kao, Hsin-Che Chiang, Kuo-Hua Pan
  • Patent number: 10818588
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Yi-Che Chiang
  • Publication number: 20200335337
    Abstract: A semiconductor device includes a gate electrode, spacers and a hard mask structure. The spacers are disposed on opposite sidewalls of the gate electrode. The hard mask structure includes a first hard mask layer and a second hard mask layer. A lower portion of the first hard mask layer is disposed between the spacers and on the gate electrode, and a top portion of the first hard mask layer is surrounded by the second hard mask layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 10755970
    Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Li Huang, Chun-Sheng Liang, Jeng-Ya David Yeh
  • Patent number: 10741558
    Abstract: A method of forming a semiconductor device includes providing a fin extruding from a substrate, the fin having first epitaxial layers alternating with second epitaxial layers, the first epitaxial layers including a first semiconductor material, the second epitaxial layers including a second semiconductor material different from the first semiconductor material; etching sidewalls of at least one of the second epitaxial layers in a channel region of the fin, such that a width of the at least one of the second epitaxial layers in the channel region after etching is smaller than a width of the first epitaxial layers contacting the at least one of the second epitaxial layers; and forming a gate stack over of the fin, the gate stack engaging both the first epitaxial layers and the second epitaxial layers.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Publication number: 20200251414
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Yi-Che Chiang
  • Patent number: 10714342
    Abstract: Semiconductor devices and method of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate structure, a plug and a hard mask structure. The gate structure is disposed over the substrate. The plug is disposed over and electrically connected to the gate structure. The hard mask structure is disposed over the gate structure and includes a first hard mask layer and a second hard mask layer. The first hard mask layer surrounds and is in contact with the plug. The second hard mask layer surrounds the first hard mask layer and has a bottom surface at a height between a top surface and a bottom surface of the first hard mask layer. A material of the first hard mask layer is different from a material of the second hard mask layer.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 10685868
    Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 16, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
  • Publication number: 20200152772
    Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Ju-Li Huang, Chun-Sheng Liang, Ming-Chi Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang
  • Publication number: 20200152521
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20200105577
    Abstract: A semiconductor device includes a substrate, a gate stack over the substrate, an insulating structure over the gate stack, a conductive via in the insulating structure, and an contact etch stop layer (CESL) over the insulating structure. The insulating structure has an air slit therein. The conductive via is electrically connected to the gate stack. A portion of the CESL is exposed in the air slit.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Sheng LIANG, Wei-Chih KAO, Hsin-Che CHIANG, Kuo-Hua PAN
  • Publication number: 20200091345
    Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over the first spacer. The method for forming a FinFET device structure further includes etching the second spacer to form a gap and forming a mask layer over the gate structure and the first spacer after the gap is formed. In addition, the mask layer extends into the gap in such a way that the mask layer and the fin structure are separated by an air gap in the gap.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Inventors: Wen-Li CHIU, Hsin-Che CHIANG, Chun-Sheng LIANG, Kuo-Hua PAN