Patents by Inventor Hsin Cheng

Hsin Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240414876
    Abstract: A wireless charging device includes a casing, a wireless charging module, an air guide and a fan assembly. The casing has an interior space and an opening communicating with the interior space. The wireless charging module is disposed in the interior space. The wireless charging module has a through hole. The air guide is located in the interior space and penetrates through the through hole and the opening. The air guide and an inner surface of the opening are spaced apart from each other so as to form an inlet slot, the air guide has an inlet, a channel and an outlet, and the inlet communicates with the interior space through the channel, the outlet and the inlet slot. The fan assembly is disposed on the casing and drives air to pass through the inlet, the channel, the outlet and the inlet slot and enter into the interior space.
    Type: Application
    Filed: August 17, 2023
    Publication date: December 12, 2024
    Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Chi-Cheng HSIAO, Hsin-Cheng CHU
  • Publication number: 20240413087
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Application
    Filed: July 31, 2024
    Publication date: December 12, 2024
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Publication number: 20240413286
    Abstract: Display devices are provided. The display device includes a substrate, a plurality of light-emitting elements, a back plate, and a carrier. The substrate has a first thermal expansion coefficient. The plurality of light-emitting elements is disposed on the substrate. The back plate is disposed corresponding to the substrate and has a second thermal expansion coefficient. The carrier is disposed between the substrate and the back plate and has a third thermal expansion coefficient. The absolute value of the difference between the third thermal expansion coefficient and the first thermal expansion coefficient is less than or equal to the absolute value of the difference between the third thermal expansion coefficient and the second thermal expansion coefficient.
    Type: Application
    Filed: May 8, 2024
    Publication date: December 12, 2024
    Inventors: Li-Wei SUNG, Chieh-Tse YANG, Hsin-Cheng CHEN
  • Patent number: 12167526
    Abstract: An extreme ultraviolet (EUV) photolithography system generates EUV light by irradiating droplets with a laser. The system includes a droplet generator with a nozzle and a piezoelectric structure coupled to the nozzle. The generator outputs groups of droplets. A control system applies a voltage waveform to the piezoelectric structure while the nozzle outputs the group of droplets. The waveform causes the droplets of the group to have a spread of velocities that results in the droplets coalescing into a single droplet prior to being irradiated by the laser.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Kuang Sun, Cheng-Hao Lai, Yu-Huan Chen, Wei-Shin Cheng, Ming-Hsun Tsai, Hsin-Feng Chen, Chiao-Hua Cheng, Cheng-Hsuan Wu, Yu-Fa Lo, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: 12166724
    Abstract: A method of channel state information (CSI) reporting by a first user equipment (UE) is disclosed. The method comprises receiving, from a base station (BS), a radio resource control (RRC) message to configure a first priority level for a logical channel; performing a sidelink (SL) communication with a second UE; generating a Medium Access Control (MAC) control element (CE) for a CSI report for the SL communication with a second priority level in a fixed value; determining a prioritization between the MAC CE including the CSI report and data from the logical channel according to the fixed value of the second priority level and the first priority level; and transmitting, to the second UE or the BS, at least one of the MAC CE and the data from the logical channel based on the determined prioritization.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 10, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yu-Hsin Cheng, Mei-Ju Shih, Hung-Chen Chen, Yung-Lan Tseng, Chia-Hao Yu
  • Patent number: 12165975
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Publication number: 20240400691
    Abstract: This disclosure relates to protein complexes targeting CD47, PD-L1, and/or TGF?, and methods of use thereof. In one aspect, the protein complexes include a CD47-binding domain having all or a portion of the SIRP? extracellular region; a PD-L1-binding domains having a VHH that binds to PD-L1; and optionally a TGF?-binding domain having all or a portion of the TGFBRII extracellular region.
    Type: Application
    Filed: July 12, 2024
    Publication date: December 5, 2024
    Inventors: Jiin-Tarng WANG, Han-Fang TENG, Yun-Chih CHENG, Pan-Hsien KUO, Chieh-Hsin HO, Wei-Tse SUN, Chia-Zhen WU, Tsai-Kuei SHEN, Chi-Ling TSENG, Zong Sean JUO
  • Publication number: 20240404480
    Abstract: An electronic device includes a substrate, visible light units, infrared light units, and a light sensor. The substrate includes a first area and a second area. The visible light units are disposed on the first substrate. The infrared light units are disposed on the first substrate and adjacent to the visible light units. A part of the infrared light units is disposed in the first area, and another part of the infrared light units is disposed in the second area. The light sensor is disposed between the first area and the second area and detects infrared light. The first area has a first infrared light unit density. The second area has a second infrared light unit density. The first infrared light unit density is different to the second infrared light unit density.
    Type: Application
    Filed: May 1, 2024
    Publication date: December 5, 2024
    Applicants: Innolux Corporation, CARUX TECHNOLOGY PTE. LTD.
    Inventors: Yu-Hsuan Hsiao, Ming-Hui Chu, Hsin-Cheng Hung, Li-Wei Sung
  • Patent number: 12160972
    Abstract: A hard disk bracket configured to be installed on a case includes a tray, a base, a handle, a pin, and a latch. The tray has an accommodating space. The base is connected to the tray. The handle is disposed in the base and has a first slide part detachably fastened with the base. The pin is disposed through the handle and the base. The latch is disposed in the base and is detachably fastened with the case. The latch is fastened with the handle and has a second slide part penetrating the handle for extending outside the base.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: December 3, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Wei-Cheng Liu, Hsin-Kai Chuang
  • Publication number: 20240393674
    Abstract: An extreme ultraviolet mask includes a substrate, a reflective multilayer stack over the substrate, a capping layer over the reflective multilayer stack, a patterned absorber layer over a first portion of the capping layer, and a magnetic layer over a second portion of the capping layer around the first portion.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Kevin TANADY, Pei-Cheng HSU, Ta-Cheng LIEN, Tzu-Yi WANG, Hsin-Chang LEE
  • Publication number: 20240393673
    Abstract: A method of scanning a substrate and determining scratches of the substrate includes transmitting a converging beam of light that comprises multiple wavelengths to the substrate. Each wavelength of the multiple wavelengths focuses at a different distance in a focus interval around and including a surface of the substrate. The method also includes receiving reflected light from the surface of the substrate and determining a height or depth of the surface of the substrate based on a wavelength of the reflected light having a highest intensity.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Cheng CHEN, ShinAn KU, Ting-Hao HSU, Hsin-Chang LEE
  • Publication number: 20240395858
    Abstract: A semiconductor device includes a first channel structure extending along a first lateral direction and a second channel structure extending along the first lateral direction. The second channel structure is spaced apart from the first channel structure. The semiconductor device further includes a high-k dielectric structure extending along the first lateral direction and disposed between the first and second channel structures. The high-k dielectric structure has a bottom surface that comprises a bottommost portion and at least a first plateau portion elevated from the bottommost portion.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Huang, Chia-Cheng Chao, Yu-Wen Wang
  • Publication number: 20240394440
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Yuan TING, Hsin-Cheng Chen, Sandeep Kumar Goel, Mei Wong, Yun-Han Lee
  • Patent number: 12151427
    Abstract: A housing structure manufacturing method and an electronic device are provided. The housing structure manufacturing method includes providing a plurality of memory polymeric materials, heating the plurality of memory polymeric materials, and forming the housing structure having a first morphology by printing the plurality of memory polymeric materials that are heated.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 26, 2024
    Assignee: ADATA TECHNOLOGY CO., LTD.
    Inventors: Luca Di Fiore, Shih-Huang Tsai, Chih-Chun Huang, Hsin-Cheng Hsu
  • Patent number: 12153339
    Abstract: A pellicle for protecting a photomask from contaminant particles is provided. The pellicle includes a pellicle membrane containing at least one porous film. The at least one porous film includes a network of a plurality of nanotubes. At least one nanotube of the plurality of nanotubes includes a core nanotube and a shell nanotube surrounding the core nanotube. The core nanotube includes a material different from the shell nanotube. The pellicle further includes a pellicle border attached to the pellicle membrane along a peripheral region of the pellicle membrane and a pellicle frame attached to the pellicle border.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 12153337
    Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a patterned absorber layer on the reflective multilayer stack is provided. The patterned absorber layer includes an alloy comprising tantalum and at least one alloying element. The at least one alloying element includes at least one transition metal element or at least one Group 14 element.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Hsin-Chang Lee
  • Publication number: 20240385506
    Abstract: In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang LEE, Chia-Jen CHEN, Pei-Cheng HSU, Ta-Cheng LIEN
  • Publication number: 20240385111
    Abstract: A mask characterization method comprises measuring an interference signal of a reflection or transmission mask for use in lithography; and determining a quality metric for the reflection or transmission mask based on the interference signal. A mask characterization apparatus comprises a light source arranged to illuminate a reflective or transmissive mask with light whereby mask-reflected or mask-transmitted light is generated; an optical grating arranged to convert the mask-reflected or mask-transmitted light into an interference pattern; and an optical detector array arranged to generate an interference signal by measuring the interference pattern.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chien-Cheng Chen, Ping-Hsun Lin, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Publication number: 20240387544
    Abstract: An integrated circuit (IC) device includes first and second power rails extending in a first direction, a first plurality of active areas extending in the first direction, and a second plurality of active areas extending in the first direction and offset from the first plurality of active areas in the first direction. The first power rail is electrically connected to first active areas of each of the first and second pluralities of active areas, the second power rail is electrically connected to second active areas of each of the first and second pluralities of active areas, the first plurality of active areas includes a third active area located between the first and second active areas and electrically connected to the second power rail, and the first and second active areas of the second plurality of active areas are adjacent active areas of the second plurality of active areas.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Xuan HUANG, Shih-Wei PENG, Te-Hsin CHIU, Hou-Yu CHEN, Kuan-Lun CHENG, Jiann-Tyng TZENG
  • Publication number: 20240384410
    Abstract: A plasma enhanced atomic layer deposition (PEALD) system includes a process chamber. A target substrate is supported in the process chamber. A grid is positioned in the process chamber above the target substrate. The grid includes a plurality of apertures extending from a first side of the grid to a second side of the grid. During a PEALD process, a plasma generator generates a plasma. The energy of the plasma is reduced by passing the plasma through the apertures in the grid prior to reacting the plasma with the target substrate.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Hao LEE, Pei-Cheng HSU, Hsin-Chang LEE