Patents by Inventor Hsin Cheng

Hsin Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250072100
    Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chien-Te TU, Hsin-Cheng LIN, Chee-Wee LIU
  • Publication number: 20250065380
    Abstract: A dry cleaning device adapted to clean a container component of a container of a semiconductor manufacturing process and adapted to clean the container component by carbon dioxide snowflakes. The dry cleaning device can first inspect the container component before and after cleaning, clean the container component by carbon dioxide snowflakes according to a predetermined cleaning working set, and forwards the container component to a next workstation once the cleaning of the container component is complete. The dry cleaning device is adapted to clean a container of a semiconductor manufacturing process in a fast and effective manner without involving any liquid solvents.
    Type: Application
    Filed: August 1, 2024
    Publication date: February 27, 2025
    Applicant: GUDENG PRECISION INDUSTRIAL CO., LTD.
    Inventors: MING-CHIEN CHIU, CHIA-HO CHUANG, HSIN-MIN HSUEH, YEN-CHENG TU
  • Publication number: 20250068060
    Abstract: A method includes placing a photomask having a contamination on a surface thereof in a plasma processing chamber. The contaminated photomask is plasma processed in the plasma processing chamber to remove the contamination from the surface. The plasma includes oxygen plasma or hydrogen plasma.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Fu YANG, Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
  • Patent number: 12235586
    Abstract: Impurities in a liquefied solid fuel utilized in a droplet generator of an extreme ultraviolet photolithography system are removed from vessels containing the liquefied solid fuel. Removal of the impurities increases the stability and predictability of droplet formation which positively impacts wafer yield and droplet generator lifetime.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hao Lai, Ming-Hsun Tsai, Hsin-Feng Chen, Wei-Shin Cheng, Yu-Kuang Sun, Cheng-Hsuan Wu, Yu-Fa Lo, Shih-Yu Tu, Jou-Hsuan Lu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20250057313
    Abstract: A slide rail assembly includes a first rail, a second rail, an elastic member, a movable member and an electronic module. The second rail is movable relative to the first rail. When the second rail is located at a retracted position relative to the first rail and when the movable member is in a locking state, the elastic member is configured to be locked to accumulate the elastic force. The electronic module includes a driving device configured to drive the movable member to switch from the locking state to an unlocking state, in order to release the elastic force of the elastic member, such that the second rail is moved from the retracted position along an opening direction relative to the first rail in response to the elastic force of the elastic member.
    Type: Application
    Filed: February 7, 2024
    Publication date: February 20, 2025
    Inventors: KEN-CHING CHEN, CHUN-TA LIU, HSIN-CHENG SU, CHIH-YUAN CHANG, SHU-CHEN LIN
  • Publication number: 20250063866
    Abstract: A display apparatus includes a driving backplane, a plurality of light emitting components, a first bank layer and a plurality of scattering particles. The first bank layer is disposed on the driving backplane. The first bank layer has a plurality of first openings and a plurality of oblique surfaces defining the first openings. The light emitting components respectively overlap with the first openings of the first bank layer. The scattering particles are disposed on a plurality of light emitting surfaces of the light emitting components. A plurality of air gaps exist between the scattering particles and the oblique surfaces of the first bank layer.
    Type: Application
    Filed: December 27, 2023
    Publication date: February 20, 2025
    Inventors: Chun-Chieh Li, Sheng-Ming Huang, Han-Sheng Nian, Yu-Cheng Shih, Hsin-Hung Li
  • Publication number: 20250062082
    Abstract: An illuminated touchpad includes a panel, a light guide layer and a circuit board. The panel includes a first light transmitting region and a second light transmitting region. The light guide layer includes a first light guide region and a second light guide region. The circuit board includes a controller, a touch module, a first light source and a second light source. The controller controls the first light source to emit light, such that the first light guide region guides the light emitted by the first light source to the first light transmitting region. When the touch module senses that the first light transmitting region is touched, the controller controls the second light source to emit light, such that the second light guide region guides the light emitted by the second light source to the second light transmitting region.
    Type: Application
    Filed: August 14, 2024
    Publication date: February 20, 2025
    Applicant: DARFON ELECTRONICS CORP.
    Inventors: Heng-Yi Huang, Chao-Yu Chen, Hsin-Cheng Ho
  • Publication number: 20250063777
    Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung TSAI, Chih-Hsin KO, Clement Hsing Jen WANN, Ya-Yun CHENG
  • Patent number: 12227759
    Abstract: A temperature-sensitive cell culture composition is provided. The temperature-sensitive cell culture composition includes a hydrogel, a cellulose, a gelatin and a collagen. Based on 1 part by weight of the collagen, a content of the hydrogel is between 0.03 parts by weight and 60 parts by weight, a content of the cellulose is between 150 parts by weight and 360 parts by weight, and a content of the gelatin is between 21 parts by weight and 12 parts by weight. In addition, a method for using the temperature-sensitive cell culture composition, a method for forming the temperature-sensitive cell culture composition, and a use of the temperature-sensitive cell culture composition are also provided.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 18, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Jung Lu, Jing-En Huang, Liang-Cheng Su, Hsin-Hsin Shen, Yuchi Wang, Ying-Hsueh Chao, Li-Hsin Lin, Hsiu-Hua Huang
  • Publication number: 20250056550
    Abstract: Uplink transmission performed by a UE is provided. The UE receives configured grant (CG) configurations for allocating a group of Physical Uplink Shared Channel (PUSCH) durations in a bandwidth part (BWP), each configured grant configuration having a priority level corresponding to the allocated PUSCH duration, wherein at least two of the PUSCH durations in the group overlap in a time domain; identifies a set of PUSCH durations for transmitting a medium access control (MAC) protocol data unit (PDU) generated from available data from the group of PUSCH durations; selects a PUSCH duration from the identified set of PUSCH durations as a prioritized PUSCH duration based on a comparison of the priority levels corresponding to the identified set of PUSCH durations; and transmits the MAC PDU, via the transceiver, on the prioritized PUSCH duration.
    Type: Application
    Filed: August 15, 2024
    Publication date: February 13, 2025
    Inventors: Heng-Li Chin, Chia-Hung Wei, Wan-Chen Lin, Yu-Hsin Cheng, Chie-Ming Chou
  • Publication number: 20250054536
    Abstract: A memory device includes a memory array, a first reference voltage circuit, a first read voltage control circuit and a first write voltage control circuit. The first reference voltage circuit is configured to provide a first reference voltage signal having a first voltage level to the memory array. The first read voltage control circuit is configured to adjust the first reference voltage signal to a second voltage level when the memory array is read. The first write voltage control circuit is configured to adjust the first reference voltage signal to a third voltage level when the memory array is written. The second voltage level is higher than the first voltage level, and the third voltage level is lower than the first voltage level.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Tao CHOU, Hsin-Cheng LIN, Jih-Chao CHIU, Chee-Wee LIU
  • Publication number: 20250056782
    Abstract: A method includes forming a first pull-up transistor and a first pass-gate transistor over a substrate at a first level height, the first pull-up and first pass-gate transistors being of a dual port static random access memory (SRAM) cell; forming a first pull-down transistor and a second pass-gate transistor of the dual port SRAM cell over the substrate at a second level height; forming a second pull-down transistor and a third pass-gate transistor of the dual port SRAM cell over the substrate at a third level height; forming a second pull-up transistor and a fourth pass-gate transistor of the dual port SRAM cell over the substrate at a fourth level height.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung University
    Inventors: Tao CHOU, Hsin-Cheng LIN, Ching-Wang YAO, Li-Kai WANG, Chee-Wee LIU, Chenming HU
  • Patent number: 12225527
    Abstract: A method for a user equipment (UE) for performing a hybrid automatic repeat request (HARQ) codebook generation operation for downlink transmission(s) is disclosed. The method comprises receiving, from a base station, a dynamic scheduling configuration for HARQ feedback operation; receiving, from the base station, a scheduling signaling for a first physical downlink shared channel (PDSCH) reception with a first HARQ state feedback for the first PDSCH reception being disabled; and generating, for the HARQ feedback operation, a HARQ codebook excluding a first HARQ state for the first PDSCH reception.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: February 11, 2025
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Chia-Hao Yu, Chien-Chun Cheng, Wan-Chen Lin, Yu-Hsin Cheng
  • Patent number: 12225723
    Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 11, 2025
    Assignee: IOTMEMORY TECHNOLOGY INC.
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng
  • Patent number: 12225276
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a first holder, a fixed portion, a first driving assembly, and a first stopping assembly. The first holder is used for connecting to an optical element. The first holder is movable relative to the fixed portion. The first driving assembly is used for driving the first holder to move relative to the fixed portion. The first stopping assembly is used for restricting the movable range of the first holder relative to the fixed portion.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: February 11, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Hsiao-Hsin Hu, Shu-Shan Chen, Chao-Chang Hu, Pai-Jui Cheng, Chieh-An Chang
  • Patent number: 12220710
    Abstract: A contactless selection device, a light triggering structure thereof, and a biological particle selection apparatus are provided. The light triggering structure includes a first substrate, a first electrode layer formed on the first substrate, a photodiode layer formed on the first electrode layer, and an insulating layer that covers the photodiode layer. The photodiode layer has a thickness within a range from 1 ?m to 3 ?m, and includes a first doped layer, an I-type layer, and a second doped layer, which are sequentially stacked from the first electrode layer. The second doped layer includes a plurality of triggering pads spaced apart from each other. Each of the triggering pads has a width within a range from 3 ?m to 7 ?m, and a distance between any two of the triggering pads adjacent to each other is less than or equal to 2 ?m.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 11, 2025
    Assignee: CYTOAURORA BIOTECHNOLOGIES, INC.
    Inventors: Chung-Er Huang, Sheng-Wen Chen, Hsin-Cheng Ho
  • Patent number: 12224209
    Abstract: A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chao, Hsin-Chieh Huang, Yu-Wen Wang
  • Patent number: 12225161
    Abstract: An example electronic device includes a network communication interface to connect to a conference server, a central control device communication interface to connect to a local central control device, a microphone and a processor. The processor is to receive audio at the microphone and send the audio to the local central control device and to the conference server. The processor is to send the audio to the local central control device such that it is received by a nearby electronic device before the audio is received from the conference server by the nearby electronic device.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: February 11, 2025
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: He-Di Liu, Ting Fong Wang, Hsin-Chih Lin, Xin-Chang Chen, Yao Cheng Yang
  • Publication number: 20250048269
    Abstract: Some of the present implementations provide a method for a user equipment (UE) for receiving a power saving signal. The UE receives, from a base station, a first power saving signal that includes a minimum scheduling offset restriction between a physical downlink control channel (PDCCH) and a physical uplink shared channel (PUSCH). The UE receives a first downlink control information (DCI) that includes a second power saving signal for activating the minimum scheduling offset restriction. The UE determines an application delay indicating a time duration between receiving the second power saving signal and applying the minimum scheduling offset restriction based on a predefined value. The UE applies the minimum scheduling offset restriction to a first scheduling offset between the PDCCH and the PUSCH transmission after the application delay.
    Type: Application
    Filed: August 15, 2024
    Publication date: February 6, 2025
    Inventors: Yu-Hsin Cheng, Chie-Ming Chou, Wan-Chen LIn, Tsung-Hua Tsai
  • Publication number: 20250048411
    Abstract: A method, performed by a User Equipment (UE), for Uplink (UL) transmission management includes the UE determining a default spatial domain transmission filter for an UL resource according to at least one Quasi Co-Location (QCL) parameter of a Control Resource Set (CORESET) after determining that the UL resource is not configured with a spatial domain transmission filter and a pathloss reference Reference Signal (RS) resource, and transmitting the UL resource by applying the default spatial domain transmission filter.
    Type: Application
    Filed: August 12, 2024
    Publication date: February 6, 2025
    Inventors: Chia-Hao Yu, Yu-Hsin Cheng