Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

Abstract: A redistribution structure including a first redistribution layer is provided. The first redistribution layer includes a dielectric layer; at least one conductive structure located in the dielectric layer, wherein the at least one conductive structure has a width L; and at least one dummy structure located adjacent to the at least one conductive structure and located in the dielectric layer, and the at least one dummy structure has a width D, wherein there is a gap width S between the at least one dummy structure and the at least one conductive structure, and a degree of planarization DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1?(h/T)]*100%, and h refers to a difference between a highest height and a lowest height of a top surface of the dielectric layer; and T refers to a thickness of the at least one conductive structure.

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

Abstract: A display control device includes a detector, a frequency adjusting signal generator, a clock generator and an output timing generator. The detector compares an input field reference signal with an output field reference signal to determine a time difference signal. The frequency adjusting signal generator outputs a frequency adjusting signal. The clock generator outputs a clock according to the frequency adjusting signal. The output timing generator generates an output field synchronization signal according to the clock. The clock generator adjusts the frequency of the clock according to the frequency adjusting signal.

Abstract: A display control device includes a detector, a frequency adjusting signal generator, a clock generator and an output timing generator. The detector compares an input field reference signal with an output field reference signal to determine a time difference signal. The frequency adjusting signal generator outputs a frequency adjusting signal. The clock generator outputs a clock according to the frequency adjusting signal. The output timing generator generates an output field synchronization signal according to the clock. The clock generator adjusts the frequency of the clock according to the frequency adjusting signal.

Abstract: A wearable medical examination and treatment device and system are introduced. The wearable medical examination and treatment device includes an enclosing unit, test electrode unit, ground electrode, processing module and transmission module which are disposed at the enclosing unit. The enclosing unit encloses a human body part of a subject and is fixed thereto by positioning holes disposed at the enclosing unit. The test electrode unit and ground electrode are in contact with acupoint testing points of the human body part. The processing module is electrically connected to the test electrode unit and ground electrode and sends testing and treating electrical signals according to testing and treating instructions. The transmission module is electrically connected to the processing module to send impedance signals to an external electronic device so as for the subject's physiological information to be displayed on the electronic device according to the impedance signals.

Abstract: The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command signals are generated and expanding a latching interval of a part of address signals, not only the memory controller is enabled to control the DDR memory modules in a functional manner to further overcome issues of conventionally small latching intervals, but also system stability and access performance are reinforced as the memory access clock speed continue to increase.

Abstract: The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command signals are generated and expanding a latching interval of a part of address signals, not only the memory controller is enabled to control the DDR memory modules in a functional manner to further overcome issues of conventionally small latching intervals, but also system stability and access performance are reinforced as the memory access clock speed continue to increase.

Abstract: A chip with flexible pad sequence manipulation is provided. The chip can be a memory controller, and includes a hub unit. The hub unit, formed by a gate array, is placed in a hub region predetermined during placing and routing procedures, and is capable of supporting re-placing and re-routing for changing interior interconnections and a pad sequence of the chip.

Abstract: A memory device includes a plurality of memory cells each including a recordable layer between two metal layers, the recordable layer including a first sub-cell and a second sub-cell. Each memory cell is constructed and designed to change from an as-deposited state to an initialized state upon application of an initialization signal, from the initialized state to a first inscribed state upon application of a first write signal, and from the initialized state to a second inscribed state upon application of a second write signal. The memory cell has a resistor-like current-voltage (I-V) characteristic when in the as-deposited state, a diode-like I-V characteristic when in the initialized state, and resistor-like I-V characteristics when in the first and second inscribed states for voltages within a predetermined range.

Abstract: A memory device includes memory cells each having a recordable layer between two metal layers, each memory cell being constructed and designed to change from a first state to a second state upon application of an initialization signal, and change from the second state to a third state upon application of a write signal. For a voltage within a specified range that is applied across the two metal layers, the memory cell has a lower resistance in the first state than in the second state, and has a higher resistance in the second state than in the third state.

Abstract: A memory device includes memory cells each having a recordable layer between two metal layers, each memory cell being constructed and designed to change from a first state to a second state upon application of an initialization signal, and change from the second state to a third state upon application of a write signal. For a voltage within a specified range that is applied across the two metal layers, the memory cell has a lower resistance in the first state than in the second state, and has a higher resistance in the second state than in the third state.

Abstract: A memory device includes a plurality of memory cells each including a recordable layer between two metal layers, the recordable layer including a first sub-cell and a second sub-cell. Each memory cell is constructed and designed to change from an as-deposited state to an initialized state upon application of an initialization signal, from the initialized state to a first inscribed state upon application of a first write signal, and from the initialized state to a second inscribed state upon application of a second write signal. The memory cell has a resistor-like current-voltage (I-V) characteristic when in the as-deposited state, a diode-like I-V characteristic when in the initialized state, and resistor-like I-V characteristics when in the first and second inscribed states for voltages within a predetermined range.

Abstract: A recordable medium includes a recordable structure including a first layer having a reflectivity R1 and a transmissivity T1, a second layer having a transmissivity T2, and a third layer having a reflectivity R3. The second layer is disposed between the first and third layers and has a thickness that is less than a Debye length determined based on a charge density of the second layer. The recordable structure has an overall reflectivity Rsum that is greater than R1+T12*T22*R2.

Abstract: A recordable medium includes an inscription layer and at least one contrast inverting layer. The inscription layer has at least a first sub-layer and a second sub-layer that combine upon application of a write power. The inscription layer has a reflectivity R1 with respect to a read beam before application of the write power and a reflectivity R2 after application of the write power, and R1<R2. The at least one contrast inverting layer does not combine with the first and second sub-layers of the inscription layer upon application of the write power. The at least one contrast inverting layer and the inscription layer together have a reflectivity R3 before application of the write power and a reflectivity R4 after application of the write power, and R3>R4.

Abstract: A recordable medium includes a first recordable structure, a second recordable structure, and a spacer layer positioned between the first and second recordable structures. The first recordable structure has a transmissivity with respect to a read beam that increases upon application of a write power to the first recordable structure. The second recordable structure has an optical property that changes upon application of a write power to the second recordable structure.

Abstract: A recordable medium includes an inscription layer and a contrast enhancing layer. The inscription layer has at least two sub-layers that combine upon application of a write power, the inscription layer having a reflectivity R1 before application of the write power and a reflectivity R2 after application of the write power. The contrast enhancing layer does not combine with the sub-layers of the inscription layer upon application of the write power. The contrast enhancing layer and the inscription layer together have a reflectivity R3 before application of the write power and a reflectivity R4 after application of the write power, and |R4?R3|>|R2?R1|.

Abstract: A recordable medium includes a first recordable structure, a second recordable structure, and a spacer layer positioned between the first and second recordable structures. The first recordable structure has a transmissivity with respect to a read beam that increases upon application of a write power to the first recordable structure. The second recordable structure has an optical property that changes upon application of a write power to the second recordable structure.

Abstract: A recordable medium includes an inscription layer and at least one contrast inverting layer. The inscription layer has at least a first sub-layer and a second sub-layer that combine upon application of a write power. The inscription layer has a reflectivity R1 with respect to a read beam before application of the write power and a reflectivity R2 after application of the write power, and R1<R2. The at least one contrast inverting layer does not combine with the first and second sub-layers of the inscription layer upon application of the write power. The at least one contrast inverting layer and the inscription layer together have a reflectivity R3 before application of the write power and a reflectivity R4 after application of the write power, and R3>R4.