Patents by Inventor Hsin-Chieh Huang

Hsin-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180174937
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 21, 2018
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20180108742
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Application
    Filed: November 20, 2017
    Publication date: April 19, 2018
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Patent number: 9941216
    Abstract: A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Chien-Chia Chiu, Hsin-Chieh Huang, Tsung-Shu Lin, Pei-Ti Yu
  • Publication number: 20180096942
    Abstract: An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.
    Type: Application
    Filed: October 26, 2017
    Publication date: April 5, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Publication number: 20180096939
    Abstract: A package structure is provided. The package structure includes a molding compound. The package structure also includes an integrated circuit chip having a chip edge in the molding compound. The package structure further includes a passivation layer below the integrated circuit chip and the molding compound. In addition, the package structure includes a redistribution layer in the passivation layer. The package structure also includes first bumps electrically connected to the integrated circuit chip through the redistribution layer. The first bumps are inside the chip edge and arranged along the chip edge. The package structure further includes second bumps electrically connected to the integrated circuit chip through the redistribution layer. The second bumps are outside the chip edge and arranged along the chip edge. The first bumps are next to the second bumps. The first and second bumps are spaced apart from the chip edge.
    Type: Application
    Filed: October 3, 2016
    Publication date: April 5, 2018
    Inventors: Ming-Yen CHIU, Hsin-Chieh HUANG, Ching-Fu CHANG
  • Publication number: 20180096943
    Abstract: An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.
    Type: Application
    Filed: October 26, 2017
    Publication date: April 5, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 9933388
    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a substrate, and a lower metal wire over the substrate and electrically coupled to the sensing device. First and second metal vias are arranged on the lower metal wire at locations set back from sidewalls of the lower metal wire, and first and second upper metal wires respectively cover top surfaces of the first and second metal vias. A dielectric structure surrounds the lower metal wire, the first and second metal vias, and the first and second upper metal wires. A sensing well has sensing surfaces that extend along an upper surface of the lower metal wire and along sidewalls of the first and second metal vias and the first and second upper metal wires.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Fei-Lung Lai, Chia-Hua Chu, Yi-Hsien Chang, Hsin-Chieh Huang
  • Publication number: 20180082917
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Application
    Filed: December 23, 2016
    Publication date: March 22, 2018
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20180080634
    Abstract: A variable focus lighting fixture includes a fixed sleeve assembly, a moveable sleeve assembly, a light emitting unit, a lens and an actuation assembly. The moveable sleeve assembly penetrates into the fixed sleeve assembly and moves relative to the fixed sleeve assembly. The light emitting unit is secured onto the fixed sleeve assembly. The lens is secured onto the moveable sleeve assembly. The actuation assembly is connected between the moveable sleeve assembly and the fixed sleeve assembly. The actuation assembly includes a spiral curve slot and a sliding pin penetrating into the spiral curve slot. When the moveable sleeve assembly rotates along a central axis of the moveable sleeve assembly, the sliding pin moves along the spiral curve slot to drive the moveable sleeve assembly to move along the axial direction thereof. Accordingly, the projection path of the light from the light emitting unit through the lens is altered.
    Type: Application
    Filed: September 21, 2016
    Publication date: March 22, 2018
    Inventors: Hsin-Chieh HUANG, Shun WANG, Shun-Wen TENG
  • Publication number: 20180082988
    Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
    Type: Application
    Filed: December 1, 2016
    Publication date: March 22, 2018
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 9922895
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 9922896
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20180076129
    Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.
    Type: Application
    Filed: January 19, 2017
    Publication date: March 15, 2018
    Inventors: HSI-KUEI CHENG, CHIH-KANG HAN, CHING-FU CHANG, HSIN-CHIEH HUANG
  • Publication number: 20180075981
    Abstract: An ether-bridged dication is provided with two monovalent cations bonded via a carbon chain having ether group(s). The ether-bridged dication, monovalent cations, and anions are contained together within an ionic liquid electrolyte which is applied to a charge storage device. The ether-bridged dication, the ionic liquid electrolyte, and the charge storage device have operational abilities at room temperatures or below, and a reachable working potential of 3.5 V.
    Type: Application
    Filed: January 26, 2017
    Publication date: March 15, 2018
    Inventors: Hsisheng TENG, I-Wen Sun, Hsin-Chieh Huang, Yung-Che Yen
  • Publication number: 20180067288
    Abstract: A device for measuring solution concentration includes housing, a catadioptric structure, an electromagnetic radiation emitter and an electromagnetic radiation detector. The housing is formed with a detecting part for receiving a solution to be detected. The catadioptric structure is received in the housing, and includes a ray entrance portion, a first total internal reflection part, a second total internal reflection part and a ray exit portion. An accommodation part corresponds to the detecting part. The emitter is disposed at one side of the ray entrance portion, and a ray sequentially passes the ray entrance portion, the detecting part, the solution to be detected, and the first total internal reflection part. Then, the ray is totally internally reflected and converged to the second total internal reflection part, and is reflected again. Finally, the ray passes the ray exit portion and is received by the detector.
    Type: Application
    Filed: October 26, 2016
    Publication date: March 8, 2018
    Inventors: HSIN-CHIEH HUANG, CHENG-YU HUANG, SHUN WANG, SHUN-WEN TENG
  • Publication number: 20180058666
    Abstract: An illumination device and the optical lens assembly thereof are provided. The illumination device includes the optical lens assembly, a light source and a driving device. The optical lens assembly includes an inner lens and an outer lens. The inner lens has a reflector having a light emission portion and a light incidence portion. An accommodating space is formed in the reflector adjacent to the light incident portion. The outer lens has a light guiding column and an outer light emission portion connected to the top of the light guiding column. The outer lens is disposed at a side of the inner lens, the light guiding column corresponds to the accommodating space, the outer light emission portion corresponds to the light emission portion. The driving device enables the outer and inner lenses to move toward or away from each other. The guiding column moves relative to the accommodating space.
    Type: Application
    Filed: October 24, 2016
    Publication date: March 1, 2018
    Inventors: HSIN-CHIEH HUANG, SHUN WANG, SHUN-WEN TENG
  • Patent number: 9905467
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Publication number: 20180025986
    Abstract: A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 25, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 9837359
    Abstract: An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Publication number: 20170345762
    Abstract: A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.
    Type: Application
    Filed: September 29, 2016
    Publication date: November 30, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Chien-Chia Chiu, Hsin-Chieh Huang, Tsung-Shu Lin, Pei-Ti Yu