Patents by Inventor Hsin-Chih Chen

Hsin-Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190244787
    Abstract: A plasma etching reaction chamber includes a casing having a receiving chamber; a base liftably installed below the receiving chamber; a first electrode and a second electrode; and a radio frequency electrode rod. The second electrode has a plurality of water channels and a bottom of the second electrode is installed with two cooling water tubes which are communicated with the plurality of water channels; upper sides of the two cooling water tubes are hidden within the driving rod and lower sides thereof extend downwards to be out of the casing so that external cooling water can flow into the cooling water tubes and then to the water channels to achieve the object of cooling.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 8, 2019
    Inventors: Wei-Chuan Chou, Zhi Kai Huang, Mu-Chun Ho, Chun-Fu Wang, Yi-Hsiang Chen, Hsin-Chih Chiu, Yao-Syuan Cheng
  • Publication number: 20190245054
    Abstract: A vertical MOS transistor includes a substrate, a metal line over the substrate, a semiconductor pillar, a gate dielectric layer surrounding the semiconductor pillar, and a metal gate surrounding the gate dielectric layer. The metal line is under a bottom surface of the semiconductor pillar. The semiconductor pillar is grown by using the bottom-up growing in low temperature to reduce turn off leakage current (Ioff), short channel effect, thermo-budget, and provide high electron mobility.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Tai-I YANG, Yung-Chih WANG, Shin-Yi YANG, Chih-Wei LU, Hsin-Ping CHEN, Shau-Lin SHUE
  • Publication number: 20190227691
    Abstract: Controlling a touch-sensitive display unit is described. In an example implementation, a physical configuration of a mobile computing device is identified. The physical configuration may be one of a clamshell mode and a tablet mode. Further, based on the physical configuration of the mobile computing device, the operational state of the touch-sensitive display unit of the mobile computing device is switched to one of an active state and an inactive state.
    Type: Application
    Filed: October 11, 2016
    Publication date: July 25, 2019
    Inventors: HSIN-HUI HUANG, SHAN-CHIH CHEN
  • Publication number: 20190229014
    Abstract: A method for fabricating a semiconductor structure is disclosed. A bit line is formed on a substrate. The bit line comprises a tungsten layer and cap layer on the tungsten layer. A low-temperature physical vapor deposition (PVD) process is performed to deposit a silicon nitride spacer layer covering the bit line and the substrate. The silicon nitride spacer layer is in direct contact with the tungsten layer. The low-temperature PVD process is performed at a temperature ranging between 200˜400° C.
    Type: Application
    Filed: February 4, 2018
    Publication date: July 25, 2019
    Inventors: Kuan-Chun Lin, Hsin-Fu Huang, Wei-Chih Chen
  • Publication number: 20190207336
    Abstract: A high density connector and a wafer group are disclosed in this invention. The high density connector includes an insulating housing, which forms a guide bracket to provide a guiding and locking function for a plug connector. The wafer group includes two signal wafers and a grounding wafer, which are adjacent to be arranged. The two adjacent signal wafers make up a group. Signal terminals of the two adjacent signal wafers can form multiple differential pairs in an edge-coupled manner, thereby reducing the loss of signal transmission and improving the quality of differential signal transmission.
    Type: Application
    Filed: November 6, 2018
    Publication date: July 4, 2019
    Inventor: Hsin Chih CHEN
  • Publication number: 20190207337
    Abstract: A wafer group and a signal terminal assembly are disclosed in this invention. The wafer group includes a first wafer and a second wafer, which are arranged side by side. The first wafer is a signal wafer and includes a first frame and multiple first signal terminals supported by the first frame. The second wafer is a signal wafer and includes a second frame and multiple second signal terminals supported by the second frame. A first middle portion of each first signal terminal and a second middle portion of the corresponding second signal terminal are configured to be coupled together in an edge-coupled manner, thereby reducing the loss of signal transmission and improving the quality of differential signal transmission.
    Type: Application
    Filed: November 6, 2018
    Publication date: July 4, 2019
    Inventor: Hsin Chih CHEN
  • Patent number: 10338364
    Abstract: A light source module including at least one optical film and a light source unit is provided. The light source unit is disposed under the at least one optical film, and a space is formed between the light source unit and the at least one optical film. The light source unit includes a plurality of light emitting elements and a plurality of secondary lenses. The light emitting elements are arranged along a direction parallel to the at least one optical film. The secondary lenses are correspondingly disposed on the light emitting elements and each of the secondary lenses has a patterned reflective layer.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: July 2, 2019
    Assignee: Coretronic Corporation
    Inventors: Fang-Ju Yeh, Chiao-Chih Yang, Hsin-Hung Lee, Chi-Lun Chen
  • Patent number: 10325993
    Abstract: A device includes a nanowire, a gate dielectric layer and a gate electrode. The nanowire has a sidewall. The gate dielectric layer surrounds the nanowire. The gate electrode surrounds the gate dielectric layer and separated from the nanowire. The gate electrode comprises a sloped sidewall inclined with respect to the sidewall of the nanowire.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
  • Publication number: 20190171060
    Abstract: A display device includes a display panel, a light shielding unit and a back plate. The display panel includes a first substrate, a second substrate and an upper polarizer. The first substrate is disposed corresponding to the second substrate. The upper polarizer is disposed on the second substrate. The light shielding unit is connected to the upper polarizer. The first substrate is disposed on the back plate.
    Type: Application
    Filed: January 22, 2019
    Publication date: June 6, 2019
    Inventors: Chien-Chih CHEN, Chia-Chun YANG, Chin-Cheng KUO, Hsin-Tien WU, Chih-Jen CHANG
  • Patent number: 10290604
    Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
  • Patent number: 10160239
    Abstract: A printer may include a printhead assembly, a clutch assembly, and/or a printer ribbon transport assembly. An example clutch assembly includes a first spool engagement member defining a first friction torque; a first friction member configured to frictionally engage the first spool engagement member; a second spool engagement member defining a second friction torque that is larger than the first fiction torque; and a second friction member configured to frictionally engage the second spool engagement member.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: December 25, 2018
    Assignee: ZIH Corp.
    Inventors: Hsin-Chih Chen, Petricia Dorinel Balcan, Randal Wong
  • Publication number: 20180174854
    Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Lin
  • Publication number: 20180151381
    Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.
    Type: Application
    Filed: May 3, 2017
    Publication date: May 31, 2018
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
  • Publication number: 20180123274
    Abstract: A double-sided pluggable combination structure is disclosed in this invention, which includes a double-sided pluggable power plug and a double-sided pluggable power socket. When the power plug and the power socket are engaged with each other, an insertion part of the power socket can enter into a receiving cavity from a plug port of the power plug by an obverse insertion mode or a reverse insertion mode, and each plug terminal of the power plug can be inserted into an insertion hole from a corresponding socket port of the power socket. An engaged portion of the plug terminal can be clamped by elastic arms of a socket terminal, thereby forming a stable electric contact between the plug terminal and the socket terminal.
    Type: Application
    Filed: March 19, 2017
    Publication date: May 3, 2018
    Applicant: Oupiin Electronic (Kunshan) Co., Ltd.
    Inventor: Hsin-chih Chen
  • Patent number: 9960514
    Abstract: A double-sided pluggable combination structure is disclosed in this invention, which includes a double-sided pluggable power plug and a double-sided pluggable power socket. When the power plug and the power socket are engaged with each other, an insertion part of the power socket can enter into a receiving cavity from a plug port of the power plug by an obverse insertion mode or a reverse insertion mode, and each plug terminal of the power plug can be inserted into an insertion hole from a corresponding socket port of the power socket. An engaged portion of the plug terminal can be clamped by elastic arms of a socket terminal, thereby forming a stable electric contact between the plug terminal and the socket terminal.
    Type: Grant
    Filed: March 19, 2017
    Date of Patent: May 1, 2018
    Assignee: OUPIIN ELECTRONIC (KUNSHAN) CO., LTD.
    Inventor: Hsin-chih Chen
  • Patent number: 9917192
    Abstract: A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 9893472
    Abstract: A pluggable connector with anti-electromagnetic interference capability is disclosed in this invention, which includes a socket housing, multiple terminal assemblies and a shielding case. The socket housing includes an insulating base and an anti-EMI block. The insulating base and the anti-EMI block can be combined together to form an upper circuit board slot and a lower circuit board slot. These terminal assemblies are mounted in the socket housing and include multiple signal terminal assemblies and multiple ground terminal assemblies, which are arranged side by side in the order of ground-signal-signal. The shielding case has an upper port and a lower port, which are respectively aligned with the upper circuit board slot and the lower circuit board slot. The pluggable connector of the present invention has a good anti-electromagnetic interference capability by an anti-EMI block.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: February 13, 2018
    Assignee: Oupiin Electronic (Kunshan) Co., Ltd.
    Inventor: Hsin Chih Chen
  • Patent number: 9893471
    Abstract: A high speed connector assembly is disclosed in this invention, including a receptacle connector and a plug connector. Two first L-shaped contact pieces of each pair of differential signal receptacle terminals are configured to be splayed apart, and two second L-shaped contact pieces of each pair of differential signal plug terminals are configured to be splayed apart too. When the receptacle connector and the plug connector are engaged with each other, a second extending section of the differential signal plug terminal is pressed onto a first side edge of the differential signal receptacle terminal, and a first extending section of the differential signal receptacle terminal is pressed onto a second side edge of the differential signal plug terminal, thereby forming a stable electrical contact therebetween.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: February 13, 2018
    Assignee: OUPIIN ELECTRONIC (KUNSHAN) CO., LTD
    Inventor: Hsin Chih Chen
  • Publication number: 20180040989
    Abstract: A high speed connector assembly is disclosed in this invention, including a receptacle connector and a plug connector. Two first L-shaped contact pieces of each pair of differential signal receptacle terminals are configured to be splayed apart, and two second L-shaped contact pieces of each pair of differential signal plug terminals are configured to be splayed apart too. When the receptacle connector and the plug connector are engaged with each other, a second extending section of the differential signal plug terminal is pressed onto a first side edge of the differential signal receptacle terminal, and a first extending section of the differential signal receptacle terminal is pressed onto a second side edge of the differential signal plug terminal, thereby forming a stable electrical contact therebetween.
    Type: Application
    Filed: March 9, 2017
    Publication date: February 8, 2018
    Inventor: Hsin Chih CHEN
  • Patent number: D840939
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: February 19, 2019
    Assignee: OUPIIN ELECTRONIC (KUNSHAN) CO., LTD.
    Inventor: Hsin Chih Chen