Abstract: A semiconductor structure includes a substrate, a conductive via and a first insulation layer. The conductive via is through the substrate. The first insulation layer is between the substrate and the conductive via. A first surface of the first insulation layer facing the substrate and a second surface of the first insulation layer facing the conductive via are extended along different directions.

Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.

Abstract: An uninterruptible power apparatus is coupled between a power grid and a load. The uninterruptible power apparatus includes a bypass path, a power conversion module, and a control module. The bypass path is coupled to the power grid through a grid terminal, and coupled to the load through a load terminal. The control module turns off a first thyristor and a second thyristor by injecting a second voltage into the load terminal during a forced commutation period. The control module calculates a magnetic flux offset amount based on an error amount between the second voltage and a voltage command, and provides a compensation command in response to the magnetic flux offset amount. The control module controls the DC/AC conversion circuit to provide a third voltage to the load terminal based on the compensation command and the voltage command.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.

Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.

Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A ground fault detection apparatus is used to detect a ground fault of a three-phase UPS apparatus. The UPS apparatus includes a first filter circuit, an AC/DC conversion circuit, a DC bus, a DC/AC conversion circuit, and a second filter circuit coupled in sequence. The ground fault detection apparatus includes a detection circuit having a first detection end and a second detection end. The first detection end is coupled to the first filter circuit and the second filter circuit, and the second detection end is coupled to an equipment grounding point. The equipment grounding point is coupled to a neutral point of a three-phase power source, and the three-phase power source is coupled to the first filter circuit. The detection circuit indicates whether the UPS apparatus has a ground fault and a location where the ground fault occurs according to a detection voltage between the first detection end and the second detection end.

Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.

Abstract: An uninterruptible power apparatus is coupled between a power grid and a load. The uninterruptible power apparatus includes a bypass path, a power conversion module, and a control module. The bypass path is coupled to the power grid through a grid terminal, and coupled to the load through a load terminal. The control module turns off a first thyristor and a second thyristor by injecting a second voltage into the load terminal during a forced commutation period. The control module calculates a magnetic flux offset amount based on an error amount between the second voltage and a voltage command, and provides a compensation command in response to the magnetic flux offset amount. The control module controls the DC/AC conversion circuit to provide a third voltage to the load terminal based on the compensation command and the voltage command.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: An uninterruptible power apparatus with a function of forced disconnection path is coupled between a grid and a load, and the uninterruptible power apparatus includes a bypass path, a power conversion module, a current detection unit, and a control module. The bypass path includes a switch unit, and the power conversion module is connected in parallel to the bypass path. The current detection unit detects a current flowing through the bypass path and transmits a current signal to the control module. The control module provides a turned-off signal to the switch unit when a first voltage of the grid is abnormal, and transmits a polarity of the current signal. The power conversion module generates a compensation amount according to the polarity, and generates an output voltage command according to the compensation amount and a voltage at an input terminal or an output terminal of the power conversion module.

Abstract: A ground fault detection apparatus is used to detect a ground fault of a three-phase UPS apparatus. The UPS apparatus includes a first filter circuit, an AC/DC conversion circuit, a DC bus, a DC/AC conversion circuit, and a second filter circuit coupled in sequence. The ground fault detection apparatus includes a detection circuit having a first detection end and a second detection end. The first detection end is coupled to the first filter circuit and the second filter circuit, and the second detection end is coupled to an equipment grounding point. The equipment grounding point is coupled to a neutral point of a three-phase power source, and the three-phase power source is coupled to the first filter circuit. The detection circuit indicates whether the UPS apparatus has a ground fault and a location where the ground fault occurs according to a detection voltage between the first detection end and the second detection end.

Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.

Abstract: The present invention discloses a high-speed signal terminal, a differential signal terminal pair and a high-speed connector assembly. The high-speed signal terminal comprises: a body portion, a U-shaped fork end, and a tail end. The differential signal terminal pair comprises a first differential signal terminal pair and a second differential signal terminal pair engaged in a criss-crossed manner, and the first differential signal terminal pair comprises two first high-speed signal terminals, and the second differential signal terminal pair comprises two second high-speed signal terminals. The high-speed connector assembly of the present invention adopts the differential signal terminal pair via a criss-crossed engaging type so that the high-speed connector assembly can be applied in a high-density and high-speed transmission environment and meet high-density and high-speed signal transmission requirement.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A method for operating a power factor correction (PFC) circuit of an uninterruptible power supply (UPS) apparatus is provided. The PFC circuit includes two T-type converters, and each of the T-type converters includes four switching tubes. The method includes: converting AC input voltage into a positive bus voltage across a first capacitor and a negative bus voltage across a second capacitor that is connected in series with the first capacitor when the UPS apparatus is operated under a normal supply mode; and controlling conduction states of the switching tubes of the T-type converters to balance the positive bus voltage and the negative bus voltage when the UPS apparatus is operated under a battery supply mode.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.