Patents by Inventor Hsin-Chun Chang

Hsin-Chun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367323
    Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu
  • Publication number: 20220335887
    Abstract: A pixel array is provided. The pixel array includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels. Each green pixel includes a light emitting diode (LED), a first transistor, a second transistor, a third transistor, and a fourth transistor. The LED receives a system low voltage. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to a second end of the first transistor and the anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to a first end of the second transistor. The fourth transistor is coupled to the anode of the light-emitting diode of an adjacent green pixel, a control terminal of the third transistor, and the anode of the light-emitting diode.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 20, 2022
    Applicant: Au Optronics Corporation
    Inventors: Ya-Jung Wang, Jing-Wun Jhang, Rong-Fu Lin, Nien-Chen Li, Hsien-Chun Wang, Che-Chia Chang, June Woo Lee, Hsin-Ying Lin, Chia-Ting Hsieh, Chien-Fu Huang, Sung-Yu Su
  • Publication number: 20220335886
    Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 20, 2022
    Applicant: Au Optronics Corporation
    Inventors: Ya-Jung Wang, Jing-Wun Jhang, Rong-Fu Lin, Nien-Chen Li, Hsien-Chun Wang, Che-Chia Chang, June Woo Lee, Hsin-Ying Lin, Chia-Ting Hsieh, Chien-Fu Huang, Sung-Yu Su
  • Publication number: 20220293528
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Application
    Filed: April 28, 2021
    Publication date: September 15, 2022
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Patent number: 11430934
    Abstract: A light-emitting device includes: a substrate, including a first edge, a second edge, a third edge and a fourth edge; a semiconductor stack formed on the substrate, comprising a first semiconductor layer, a second semiconductor layer and an active layer; a first electrode formed on the first semiconductor layer, comprising a first pad electrode; and a second electrode formed on the second semiconductor layer, comprising a second pad electrode and a second finger electrode; wherein in a top view, the first pad electrode is adjacent to a corner of the substrate that is intersected by the first and the second edges; the second finger electrode is not parallel with the third and the first edges; and a distance between the second finger electrode and the first edge increases along a direction from an end of the second finger electrode that connects the second pad electrode toward the second edge.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: August 30, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Li-Ming Chang, Tzung-Shiun Yeh, Chien-Fu Shen, Yu-Rui Lin, Chen Ou, Hsin-Ying Wang, Hui-Chun Yeh
  • Publication number: 20220269467
    Abstract: An image displaying device includes a planar display panel and a light penetrating unit. The planar display panel displays a plane image. The planar display panel at least includes a first pixel group, a second pixel group and a third pixel group. The second pixel group is located between the first pixel group and the third pixel group. When vision passes through the light penetrating unit toward the planar display panel, the vision acquires a second distance of a second imaging position within the plane image relevant to the second pixel group relative to the planar display panel being greater than a first distance of a first imaging position within the plane image relevant to the first pixel group relative to the planar display panel and a third distance of a third imaging position within the plane image relevant to the third pixel group relative to the planar display panel.
    Type: Application
    Filed: January 10, 2022
    Publication date: August 25, 2022
    Applicant: QISDA CORPORATION
    Inventors: Hao-Chun Tung, Hsin-Che Hsieh, Wei-Jou Chen, Po-Fu Wu, Yu-Fu Fan, Chih-Ming Chang
  • Publication number: 20220216165
    Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong LIN, Kuo-Yen LIU, Hsin-Chun CHANG, Tzu-Li LEE, Yu-Ching LEE, Yih-Ching WANG
  • Patent number: 11378493
    Abstract: A method for a motion test and a control host of a movable machinery are provided. The method includes: loading a first motion test program; generating, according to the first motion test program, a template file recording first coordinate information indicated by the first motion test program for the movable machinery to perform a physical motion; loading a second motion test program; reading the template file according to program information of the second motion test program and comparing second coordinate information indicated by the second motion test program for the movable machinery to perform the physical motion with the first coordinate information; and generating, according to a comparison result, a warning message reflecting that a control for the movable machinery by the second motion test program may be abnormal.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: July 5, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Chun Ho, Chin-Hui Chen, Chao-Chuang Mai, Hsin-Chang Chang
  • Publication number: 20220205875
    Abstract: A method for a motion test and a control host of a movable machinery are provided. The method includes: loading a first motion test program; generating, according to the first motion test program, a template file recording first coordinate information indicated by the first motion test program for the movable machinery to perform a physical motion; loading a second motion test program; reading the template file according to program information of the second motion test program and comparing second coordinate information indicated by the second motion test program for the movable machinery to perform the physical motion with the first coordinate information; and generating, according to a comparison result, a warning message reflecting that a control for the movable machinery by the second motion test program may be abnormal.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 30, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Chun Ho, Chin-Hui Chen, Chao-Chuang Mai, Hsin-Chang Chang
  • Patent number: 11302654
    Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Publication number: 20210375723
    Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.
    Type: Application
    Filed: January 29, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Ming-Hong HSIEH, Ming-Yih WANG, Yinlung LU
  • Publication number: 20200411452
    Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong LIN, Kuo-Yen LIU, Hsin-Chun CHANG, Tzu-Li LEE, Yu-Ching LEE, Yih-Ching WANG
  • Patent number: 10777510
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 10431541
    Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Hui Lee, Yung-Sheng Huang, Yung-Huei Lee
  • Publication number: 20180269148
    Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 20, 2018
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Hui LEE, Yung-Sheng HUANG, Yung-Huei LEE
  • Publication number: 20180151511
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Application
    Filed: January 3, 2017
    Publication date: May 31, 2018
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 9941159
    Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee
  • Publication number: 20160372368
    Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Shiou-Fan CHEN, Chwei-Ching CHIU, Yung-Huei LEE
  • Patent number: 9449919
    Abstract: A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion. The first interconnect portion has a width and a length. The second interconnect portion has a width less than the length of the first interconnect portion. The second interconnect portion is connected to the first interconnect portion. The third interconnect portion has a width less than the width of the second interconnect portion. The third interconnect portion is connected to the second interconnect portion.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee
  • Publication number: 20160240472
    Abstract: A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion. The first interconnect portion has a width and a length. The second interconnect portion has a width less than the length of the first interconnect portion. The second interconnect portion is connected to the first interconnect portion. The third interconnect portion has a width less than the width of the second interconnect portion. The third interconnect portion is connected to the second interconnect portion.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Shiou-Fan CHEN, Chwei-Ching CHIU, Yung-Huei LEE