Patents by Inventor Hsin-Chun Chang

Hsin-Chun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321487
    Abstract: A method of transferring semiconductor devices from a first substrate to a second substrate, including providing the semiconductor devices which are between the first substrate and the second substrate. The semiconductor devices include a first semiconductor device and a second semiconductor device, and the first semiconductor device and the second semiconductor device have a first gap between thereof. The first semiconductor device and the second semiconductor device are moved from the first substrate by a picking unit. The picking unit, the first semiconductor device, and the second semiconductor device are moved close to the second substrate. The picking unit has a space apart from the second substrate. The first semiconductor device and the second semiconductor device are transferred from the picking unit to the second substrate. The he first semiconductor device and the second semiconductor device on the second substrate have a second gap between thereof. The first gap and the second gap are different.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Hao-Min KU, You-Hsien CHANG, Shih-I CHEN, Fu-Chun TSAI, Hsin-Chih CHIU
  • Patent number: 10795200
    Abstract: A display device includes a display panel, a light shielding unit and a back plate. The display panel includes a first substrate, a second substrate and an upper polarizer. The first substrate is disposed corresponding to the second substrate. The upper polarizer is disposed on the second substrate. The light shielding unit is connected to the upper polarizer. The first substrate is disposed on the back plate.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 6, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Chien-Chih Chen, Chia-Chun Yang, Chin-Cheng Kuo, Hsin-Tien Wu, Chih-Jen Chang
  • Patent number: 10784427
    Abstract: A light-emitting device includes a first edge to a fourth edge; a semiconductor stack formed on a substrate, including a first semiconductor layer, a second semiconductor layer and an active layer; a first electrode formed on the first semiconductor layer, including a first pad electrode and a first finger electrode; and a second electrode formed on the second semiconductor layer, including a second pad electrode and a second finger electrode; wherein the first finger electrode is disposed at and along the first edge; and the first finger electrode includes a first overlapping portion overlapping the second finger electrode; the second finger electrode includes a second overlapping portion overlapping the first finger electrode and a non-overlapping portion that does not overlap the first finger electrode; and the second overlapping portion is not parallel with the first overlapping portion and the non-overlapping portion is not parallel with the first edge.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 22, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Li-Ming Chang, Tzung-Shiun Yeh, Chien-Fu Shen, Yu-Rui Lin, Chen Ou, Hsin-Ying Wang, Hui-Chun Yeh
  • Patent number: 10777510
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 10727309
    Abstract: A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3).
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: July 28, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
  • Patent number: 10693034
    Abstract: A method of transferring multiple semiconductor devices from a first substrate to a second substrate comprises the steps of forming the multiple semiconductor devices adhered on the first substrate, wherein the multiple semiconductor devices comprises a first semiconductor device and a second semiconductor device, and the first semiconductor device and the second semiconductor device have a first gap between thereof; separating the first semiconductor device and the second semiconductor device from the first substrate; sticking the first semiconductor device and the second semiconductor device to a surface of the second substrate, wherein the first semiconductor device and the second semiconductor device have a second gap between thereof; wherein the first gap and the second gap are different.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 23, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Hao-Min Ku, You-Hsien Chang, Shih-I Chen, Fu-Chun Tsai, Hsin-Chih Chiu
  • Patent number: 10672880
    Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 2, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (SheZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Wei-Chih Chang, I-Min Lu
  • Publication number: 20200126787
    Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang
  • Publication number: 20200020839
    Abstract: A light-emitting device includes a first edge to a fourth edge; a semiconductor stack formed on a substrate, including a first semiconductor layer, a second semiconductor layer and an active layer; a first electrode formed on the first semiconductor layer, including a first pad electrode and a first finger electrode; and a second electrode formed on the second semiconductor layer, including a second pad electrode and a second finger electrode; wherein the first finger electrode is disposed at and along the first edge; and the first finger electrode includes a first overlapping portion overlapping the second finger electrode; the second finger electrode includes a second overlapping portion overlapping the first finger electrode and a non-overlapping portion that does not overlap the first finger electrode; and the second overlapping portion is not parallel with the first overlapping portion and the non-overlapping portion is not parallel with the first edge.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Li-Ming CHANG, Tzung-Shiun YEH, Chien-Fu SHEN, Yu-Rui LIN, Chen OU, Hsin-Ying WANG, Hui-Chun YEH
  • Patent number: 10522349
    Abstract: A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang
  • Patent number: 10504927
    Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).
    Type: Grant
    Filed: December 10, 2016
    Date of Patent: December 10, 2019
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
  • Patent number: 10505092
    Abstract: A light-emitting element, includes a first edge, a second edge, a third edge and a fourth edge; a substrate; a semiconductor stack formed on the substrate, including a first semiconductor layer, a second semiconductor layer and an active layer formed therebetween; a transparent conductive layer, formed on the second semiconductor layer; a first electrode formed on the first semiconductor layer, including a first pad electrode and a first finger electrode extending from the first pad electrode; and a second electrode formed on the first second semiconductor layer, including a second pad electrode and a second finger electrode extending from the second pad electrode; wherein the first finger electrode is disposed at and along the first edge; and wherein in top view, an overlapping portions of the first finger electrode and the second finger electrode are non-parallel.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: December 10, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Li-Ming Chang, Tzung-Shiun Yeh, Chien-Fu Shen, Yu-Rui Lin, Chen Ou, Hsin-Ying Wang, Hui-Chun Yeh
  • Patent number: 10431541
    Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Hui Lee, Yung-Sheng Huang, Yung-Huei Lee
  • Publication number: 20190189850
    Abstract: A light-emitting device, includes a first semiconductor stack formed on a substrate, including a first semiconductor layer, a second semiconductor layer and an active layer formed therebetween; a first electrode formed on the first semiconductor layer; a second electrode formed on the second semiconductor layer, including a second pad electrode and a second finger electrode extending from the second pad electrode; a second current blocking region formed under the second electrode, including a second core region under the second pad electrode and a extending region under the second finger electrode; and a transparent conductive layer, formed on the second semiconductor layer and covering the extending region; wherein a contour of the second core region has a shape different from that of the second pad electrode; wherein the transparent conductive layer includes a first opening having a width wider than a width of the second pad electrode, wherein the second finger electrode includes a portion extending from th
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Inventors: Hsin-Ying WANG, Hui-Chun YEH, Li-Ming CHANG, Chien-Fu SHEN, Chen OU
  • Patent number: 10323331
    Abstract: The present disclosure provides a valuable metal selectively adsorbing electrode, including: an electrode formed by a carbon-containing material; and a protein of a bacterium of genus Tepidimonas immobilized on the electrode formed by a carbon-containing material to form the valuable metal selectively adsorbing electrode, wherein the valuable metal includes gold, palladium, silver or indium.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 18, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Ching Chung, Chia-Heng Yen, Teh-Ming Liang, Ren-Yang Horng, Min-Chao Chang, Hsin Shao, Po-I Liu, Chih-Hsiang Fang, Yin-Lung Han, Kai-Chun Fan
  • Publication number: 20190171060
    Abstract: A display device includes a display panel, a light shielding unit and a back plate. The display panel includes a first substrate, a second substrate and an upper polarizer. The first substrate is disposed corresponding to the second substrate. The upper polarizer is disposed on the second substrate. The light shielding unit is connected to the upper polarizer. The first substrate is disposed on the back plate.
    Type: Application
    Filed: January 22, 2019
    Publication date: June 6, 2019
    Inventors: Chien-Chih CHEN, Chia-Chun YANG, Chin-Cheng KUO, Hsin-Tien WU, Chih-Jen CHANG
  • Publication number: 20190164745
    Abstract: A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 30, 2019
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang
  • Publication number: 20180269148
    Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 20, 2018
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Hui LEE, Yung-Sheng HUANG, Yung-Huei LEE
  • Publication number: 20180151511
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Application
    Filed: January 3, 2017
    Publication date: May 31, 2018
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 9941159
    Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee