Patents by Inventor Hsin-Huei Wu

Hsin-Huei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8674433
    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: March 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Hsin-Huei Wu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 8575043
    Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an included angle.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 5, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Tzu-Feng Kuo, Hsin-Huei Wu, Ching-I Li, Shu-Yen Chan
  • Publication number: 20130122698
    Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Min-Ying Hsu, Hsin-Huei Wu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 8440511
    Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: May 14, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Min-Ying Hsu, Hsin-Huei Wu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Publication number: 20130052778
    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Hsin-Huei Wu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Publication number: 20130026543
    Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Inventors: Chan-Lon Yang, Tzu-Feng Kuo, Hsin-Huei Wu, Ching-I Li, Shu-Yen Chan