Patents by Inventor Hsin-Hung Liao

Hsin-Hung Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220344133
    Abstract: A method for forming a layer includes following operations. A workpiece is received in an apparatus for deposition. The apparatus for deposition includes a chamber, a pedestal disposed in the chamber to accommodate the workpiece, and a ring disposed on the pedestal. The ring includes a ring body having a first top surface and a second top surface and a barrier structure disposed between the first top surface and the second top surface. A vertical distance is defined by a top surface of the barrier structure and a top surface of the workpiece. The vertical distance is between approximately 0 mm and approximately 50 mm. A target disposed in the apparatus for deposition is sputtered. A sputtered material is deposited onto a top surface of the workpiece to form a layer. The barrier structure alters an electrical density distribution during the depositing the sputter material.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: HSIN-LIANG CHEN, WEN-CHIH WANG, CHIA-HUNG LIAO, CHENG-CHIEH CHEN, YI-MING YEH, HUNG-TING LIN, YUNG-YAO LEE
  • Publication number: 20220244802
    Abstract: A touch display apparatus including a body, a display module, a light control element, and a touch module is provided. The body has an opening. The display module is disposed in the body and is suitable for emitting a plurality of image beams toward the opening. The light control element is disposed to overlap the opening of the body and is suitable for reflecting the image beams coming from the display module to an imaging space to display an image frame of the display module. The imaging space and the display module are located on two opposite sides of the light control element. The touch module is disposed on one side of the light control element and is configured to recognize a touch operation of a user in the imaging space.
    Type: Application
    Filed: January 17, 2022
    Publication date: August 4, 2022
    Applicant: CHAMP VISION DISPLAY INC.
    Inventors: Chun-Chien Liao, Hsin-Hung Lee, Hsin-Mao Chung, Ching-Hung Chen
  • Patent number: 11233032
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien-Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 11139177
    Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang
  • Patent number: 11101232
    Abstract: A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, in which the first side surface is substantially flat, and the first corner is substantially rounded.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Jui Huang, Chung-Shi Liu, Hsin-Hung Liao, Chien-Ling Hwang
  • Patent number: 11094561
    Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang
  • Patent number: 10867890
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first semiconductor die, at least one first conductive connector disposed beside the first semiconductor die and electrically coupled to the first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die and the at least one first conductive connector, and a redistribution structure disposed on the insulating encapsulation and being in contact with the first semiconductor die and the at least one first conductive connector. A thickness of the at least one first conductive connector is less than a thickness of the insulating encapsulation.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Ling Hwang, Ching-Hua Hsieh, Hsin-Hung Liao, Sung-Yueh Wu
  • Publication number: 20200357651
    Abstract: A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly, and the support assembly includes a plurality of pin. The method includes securing an etching mask to a backside of the wafer, and the etching mask has an extending portion which covers a peripheral portion of the wafer. The etching mask has a plurality of circular bores extended along a vertical direction, and the etching mask is secured to the support assembly by connecting the circular bores and the pins. The method also includes performing a wet etching process on the backside of the wafer to foil a thinned wafer, wherein the thinned wafer has a peripheral portion with a first thickness and a central portion having a second thickness smaller than the first thickness.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Hsin-Hung LIAO, Chung-Shi LIU
  • Publication number: 20200303213
    Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Chung-Shi LIU, Hsin-Hung LIAO, Ying-Jui HUANG
  • Publication number: 20200303214
    Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Chung-Shi LIU, Hsin-Hung LIAO, Ying-Jui HUANG
  • Patent number: 10770331
    Abstract: A semiconductor device includes a carrier having a first central axis extending along a first direction and a second central axis extending along a second direction, a plurality of dies disposed on a surface of the carrier, and a plurality of scribing lines separating the plurality of dies from each other. The plurality of scribing lines include a plurality of continuous lines along the first direction and a plurality of discontinuous lines along the second direction, at least one of the plurality of continuous lines overlaps the first central axis, at least one of the plurality of discontinuous lines overlaps the second central axis. The plurality of dies are symmetrically arranged on the carrier about the first central axis and the second central axis.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • Patent number: 10727074
    Abstract: A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. A system for forming the thinned wafer is also provided.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Chung-Shi Liu
  • Publication number: 20200203270
    Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, and a redistribution structure. The semiconductor device includes a chamfer disposed on one of a plurality of side surfaces of the semiconductor device. The encapsulating material encapsulates the semiconductor device. The redistribution structure is disposed over the encapsulating material and electrically connected to the semiconductor device.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 25, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Shi Liu, Ching-Hua Hsieh, Chen-Hua Yu, Hsin-Hung Liao, Chien-Ling Hwang, Sung-Yueh Wu
  • Patent number: 10679866
    Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang
  • Publication number: 20200105689
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first semiconductor die, at least one first conductive connector disposed beside the first semiconductor die and electrically coupled to the first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die and the at least one first conductive connector, and a redistribution structure disposed on the insulating encapsulation and being in contact with the first semiconductor die and the at least one first conductive connector. A thickness of the at least one first conductive connector is less than a thickness of the insulating encapsulation.
    Type: Application
    Filed: March 5, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ling Hwang, Ching-Hua Hsieh, Hsin-Hung Liao, Sung-Yueh Wu
  • Publication number: 20200105710
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 2, 2020
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien-Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10510712
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10504870
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10438922
    Abstract: A method for mounting components on a substrate is provided. The method includes providing a positioning plate which has a plurality of through holes. The method further includes supplying components each having a longitudinal portion on the positioning plate. The method also includes performing a component alignment process to put the longitudinal portions of the components in the through holes. In addition, the method includes connecting a substrate to the components which have their longitudinal portions in the through holes and removing the positioning plate.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Hsin-Hung Liao, Yu-Ting Chiu, Ching-Hua Hsieh
  • Patent number: 10276509
    Abstract: A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hsin-Hung Liao, Hao-Yi Tsai, Chien-Ling Hwang, Wei-Sen Chang, Tsung-Hsien Chiang, Tin-Hao Kuo