Patents by Inventor Hsin-Jung Lo

Hsin-Jung Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9612615
    Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu
  • Patent number: 8836146
    Abstract: A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: September 16, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Chien-Kang Chou, Chiu-Ming Chou, Li-Ren Lin, Hsin-Jung Lo
  • Patent number: 8837872
    Abstract: A device is described which includes a waveguide structure for signal transmission and power/ground delivery The waveguide structure includes a signal transmission part for transmitting an optical signal from an illuminant device to a detector. The signal transmission part may include transparent polymer, diamond or glass. The signal transmission part is used for a waveguide. The waveguide structure further includes a power/ground delivery part surrounding the signal transmission part. The power/ground delivery part is composed of at least one metal layer. Thus, the waveguide structure can provide an optical-signal transmission with high speed and high volume through the signal transmission part, while a stable power or ground reference can be provided to multiple units through the power/ground delivery part.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: September 16, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Ping-Jung Yang, Hsin-Jung Lo, Te-Sheng Liu
  • Patent number: 8692374
    Abstract: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: April 8, 2014
    Assignee: Megit Acquisition Corp.
    Inventors: Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo
  • Publication number: 20130242500
    Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
    Type: Application
    Filed: May 1, 2013
    Publication date: September 19, 2013
    Applicant: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu
  • Patent number: 8456856
    Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: June 4, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu
  • Patent number: 8426958
    Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: April 23, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen, Chiu-Ming Chou
  • Patent number: 8399989
    Abstract: A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: March 19, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
  • Patent number: 8368193
    Abstract: A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: February 5, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo
  • Patent number: 8344524
    Abstract: This invention provides a wire bonding method, comprising providing an integrated circuit (IC) die having thereon a passivation layer and a plurality of first bonding pads exposed by respective openings in the passivation layer; forming a polymer layer on the passivation layer; forming an adhesive/barrier layer on the polymer layer; forming a metal pad layer on the adhesive/barrier layer; bonding a wire onto the metal pad layer to form a ball bond thereon; and after forming the ball bond on the metal pad layer, running the wire so as to contact the wire with a second bonding pad and forming a wedge bond thereto.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: January 1, 2013
    Assignee: Megica Corporation
    Inventors: Chiu-Ming Chou, Shih-Hsiung Lin, Mou-Shiung Lin, Hsin-Jung Lo
  • Patent number: 8319354
    Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: November 27, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin
  • Patent number: 8304766
    Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: November 6, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Huei-Mei Yen, Hsin-Jung Lo, Chiu-Ming Chou, Ke-Hung Chen
  • Publication number: 20120193785
    Abstract: Multichip packages or multichip modules may include stacked chips and through silicon/substrate vias (TSVs) formed using enclosure-first technology. Enclosure-first technology may include forming an isolation enclosure associated with a TSV early in the fabrication process, without actually forming the associated TSV. The TSV associated with the isolation enclosure is formed later in the fabrication process. The enclosure-first technology allows the isolation enclosures to be used as alignment marks for stacking additional chips. The stacked chips can be connected to each other or to an external circuit such that data input is provided through the bottom-most (or topmost) chip, data is output from the bottom-most (or topmost) chip. The multichip package may provide a serial data connection, and a parallel connection, to each of the stacked chips.
    Type: Application
    Filed: January 25, 2012
    Publication date: August 2, 2012
    Applicant: Megica Corporation
    Inventors: Mou-Shiung Lin, Ping-Jung Yang, Hsin-Jung Lo, Te-Sheng Liu, Jin-Yuan Lee
  • Patent number: 8232192
    Abstract: A bonding process includes the following process. A bump is formed on a first electric device. A patterned insulation layer is formed on a second electric device, wherein the patterned insulation layer has a thickness between 5 ?m and 400 ?m, and an opening is in the patterned insulation layer and exposes the second electric device. The bump is joined to the second electric device exposed by the opening in the patterned insulation layer.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: July 31, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Shih Hsiung Lin, Hsin-Jung Lo
  • Publication number: 20120170887
    Abstract: A device is described which includes a waveguide structure for signal transmission and power/ground delivery The waveguide structure includes a signal transmission part for transmitting an optical signal from an illuminant device to a detector. The signal transmission part may include transparent polymer, diamond or glass. The signal transmission part is used for a waveguide. The waveguide structure further includes a power/ground delivery part surrounding the signal transmission part. The power/ground delivery part is composed of at least one metal layer. Thus, the waveguide structure can provide an optical-signal transmission with high speed and high volume through the signal transmission part, while a stable power or ground reference can be provided to multiple units through the power/ground delivery part.
    Type: Application
    Filed: December 27, 2011
    Publication date: July 5, 2012
    Applicant: MEGICA CORPORATION
    Inventors: Ping-Jung Yang, Hsin-Jung Lo, Te-Sheng Liu
  • Patent number: 8193636
    Abstract: A chip assembly includes a semiconductor chip, a bump and an external circuit. The semiconductor chip includes a semiconductor substrate, a transistor in and on the semiconductor substrate, multiple dielectric layers over the semiconductor substrate, a metallization structure over the semiconductor substrate, wherein the metallization structure is connected to the transistor, and a passivation layer over the metallization structure, over the dielectric layers and over the transistor. The bump is connected to the metallization structure through an opening in the passivation layer, wherein the bump includes an adhesion/barrier layer and a gold layer over the adhesion/barrier layer. The external circuit can be connected to the bump using a tape carrier package (TCP), a chip-on-film (COF) package or a chip-on-glass (COG) assembly.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: June 5, 2012
    Assignee: Megica Corporation
    Inventors: Jin-Yuan Lee, Hsin-Jung Lo
  • Patent number: 8159074
    Abstract: A semiconductor chip includes first, second and third metal interconnects and an insulating layer over a semiconductor substrate. First, second and third openings in the insulating layer are over first, second and third contact points of the first, second and third metal interconnects, respectively. A fourth metal interconnect over the insulating layer connects the first and second contact points. The fourth metal interconnect includes a first metal layer and a second metal layer. The first metal layer is under but not at a sidewall of the second metal layer. The semiconductor chip includes a metal bump connected to the third contact point through the third opening, and a dielectric layer over the fourth metal interconnect and the insulating layer. No opening is in the dielectric layer on the fourth metal interconnect, and the metal bump has a top higher than a top surface of the dielectric layer.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: April 17, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo
  • Patent number: 8148822
    Abstract: A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: April 3, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
  • Publication number: 20120007237
    Abstract: A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.
    Type: Application
    Filed: September 19, 2011
    Publication date: January 12, 2012
    Applicant: MEGICA CORPORATION
    Inventors: Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo
  • Publication number: 20110266669
    Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer.
    Type: Application
    Filed: July 12, 2011
    Publication date: November 3, 2011
    Applicant: MEGICA CORPORATION
    Inventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin, Hsin-Jung Lo