Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.

Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.

Abstract: A control method for a nonvolatile memory device with a vertically stacked structure is provided. The nonvolatile memory device includes a substrate, a common source line formed on the substrate, and plural memory blocks disposed over the substrate. Each memory block includes a cell string connected between a bit line and the common source line. Firstly, a first memory block of the plural memory blocks is selected as an active memory block, and one of the remaining memory blocks is selected as a second memory block. Then, a ground voltage is provided to the bit line of the second memory block, and the cell string of the second memory block is conducted, so that the ground voltage is transmitted from the bit line to the common source line through the cell string.

Abstract: A control method for a nonvolatile memory device with a vertically stacked structure is provided. The nonvolatile memory device includes a substrate, a common source line formed on the substrate, and plural memory blocks disposed over the substrate. Each memory block includes a cell string connected between a bit line and the common source line. Firstly, a first memory block of the plural memory blocks is selected as an active memory block, and one of the remaining memory blocks is selected as a second memory block. Then, a ground voltage is provided to the bit line of the second memory block, and the cell string of the second memory block is conducted, so that the ground voltage is transmitted from the bit line to the common source line through the cell string.