Patents by Inventor Hsin-Wei Pan

Hsin-Wei Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145639
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Wei Cheng, Chien-Hsun Lee, Chi-Yang Yu, Hao-Cheng Hou, Hsin-Yu Pan, Tsung-Ding Wang
  • Patent number: 11126517
    Abstract: A system and method for providing system data during a power-on routine of a basic input output system. A controller is powered with an independent power source and accesses the system data. A power-on self-test routine is performed via a basic input output system. The fastest available interface of a plurality of interfaces between the basic input output system and the controller is determined. One of the plurality of interfaces is selected. The system data is sent from the controller to the basic input output system via the selected interface during the power-on self-test routine.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 21, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Ai-Chin Lee, Ching-Sui Pan, Hsin-Wei Chou, Wei-Tsung Tu
  • Patent number: 10936784
    Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Hsin-Wei Pan, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Publication number: 20210004520
    Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.
    Type: Application
    Filed: December 5, 2019
    Publication date: January 7, 2021
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Hsin-Wei Pan, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Patent number: 9218853
    Abstract: A control method for a nonvolatile memory device with a vertically stacked structure is provided. The nonvolatile memory device includes a substrate, a common source line formed on the substrate, and plural memory blocks disposed over the substrate. Each memory block includes a cell string connected between a bit line and the common source line. Firstly, a first memory block of the plural memory blocks is selected as an active memory block, and one of the remaining memory blocks is selected as a second memory block. Then, a ground voltage is provided to the bit line of the second memory block, and the cell string of the second memory block is conducted, so that the ground voltage is transmitted from the bit line to the common source line through the cell string.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 22, 2015
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chrong-Jung Lin, Hsin-Wei Pan
  • Publication number: 20150187398
    Abstract: A control method for a nonvolatile memory device with a vertically stacked structure is provided. The nonvolatile memory device includes a substrate, a common source line formed on the substrate, and plural memory blocks disposed over the substrate. Each memory block includes a cell string connected between a bit line and the common source line. Firstly, a first memory block of the plural memory blocks is selected as an active memory block, and one of the remaining memory blocks is selected as a second memory block. Then, a ground voltage is provided to the bit line of the second memory block, and the cell string of the second memory block is conducted, so that the ground voltage is transmitted from the bit line to the common source line through the cell string.
    Type: Application
    Filed: March 27, 2014
    Publication date: July 2, 2015
    Applicant: LITE-ON IT CORPORATION
    Inventors: Chrong-Jung Lin, Hsin-Wei Pan