Patents by Inventor Hsin-Yu Chiang
Hsin-Yu Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071936Abstract: Disclosed are an interposer substrate, a package structure and a manufacturing method of a package structure. In one embodiment, the interposer substrate includes a substrate, a bridge device in the substrate, a memory in the substrate and beside the bridge device and a through substrate via in the substrate and beside the bridge device and the memory.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yu Ling, Hsin-Yu LAI, Katherine H CHIANG, Chung-Te Lin
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Patent number: 10685868Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.Type: GrantFiled: August 28, 2019Date of Patent: June 16, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
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Publication number: 20190393080Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.Type: ApplicationFiled: August 28, 2019Publication date: December 26, 2019Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
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Patent number: 10460939Abstract: A patterning method includes the following steps. A second mask layer is formed on a first mask layer. A patterning process is performed to the first mask layer and the second mask layer. The first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern. A first trim process is performed to the second mask pattern. A width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process. A cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process, and an etching process is performed to the first mask pattern after the step of forming the cover layer.Type: GrantFiled: May 9, 2018Date of Patent: October 29, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Hsin-Yu Chiang
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Publication number: 20190318930Abstract: A patterning method includes the following steps. A second mask layer is formed on a first mask layer. A patterning process is performed to the first mask layer and the second mask layer. The first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern. A first trim process is performed to the second mask pattern. A width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process. A cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process, and an etching process is performed to the first mask pattern after the step of forming the cover layer.Type: ApplicationFiled: May 9, 2018Publication date: October 17, 2019Inventors: Feng-Yi Chang, Fu-Che Lee, Hsin-Yu Chiang
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Patent number: 10438842Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.Type: GrantFiled: June 8, 2018Date of Patent: October 8, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Ingtegrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
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Publication number: 20190206724Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.Type: ApplicationFiled: June 8, 2018Publication date: July 4, 2019Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
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Patent number: 10078244Abstract: A direct-lit type backlight source includes a backplate and a point light source array disposed on the backplate. A light output shape of a first optical lens employed by each of point light sources of corner regions of the point light source array and that of a second optical lens employed by each of a plurality of point light sources of the non-corner region are different. For instance, the light output shape of the first optical lens is symmetrical in a first direction and asymmetrical in a vertical second direction. Moreover, a liquid crystal television adopting the direct-lit type backlight source is provided. The light-output shape of the optical lens adopted by each of the point light sources of the respective corners is designed to illuminate the corners uncovered by light source in the prior art, which can improve optical uniformity of the corners.Type: GrantFiled: December 25, 2016Date of Patent: September 18, 2018Assignee: KAISTAR LIGHTING (XIAMEN) CO., LTD.Inventors: Jenn-Yuan Hsu, Sheng-Lung Tsai, Hsin-Yu Chiang
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Publication number: 20180211867Abstract: A method for manufacturing dual damascene structures is provided with the steps of forming a via hole through a dielectric layer, forming a sacrificial layer on the dielectric layer filling up the via hole, performing an etch process through a photoresist to form a trench in the dielectric layer, wherein in the etch process the ratio of etching selectivity between the dielectric layer and the sacrificial layer is 1:1, and the trench and the via hole forms collectively a dual damascene recess.Type: ApplicationFiled: January 10, 2018Publication date: July 26, 2018Inventors: Hsin-Yu Chiang, Feng-Yi Chang, Fu-Che Lee
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Patent number: 9765942Abstract: A LED lamp and an optical lens thereof are provided. The LED lamp includes a LED light source and an optical lens covering the LED light source. The optical lens includes a dome structure and a protrusion structure. The dome structure has an external surface. The protrusion structure is disposed protruding from the external surface and includes oppositely-disposed first and second side surfaces. The first side surface includes first and second optical surfaces. The second side surface includes a third optical surface. The second optical surface is connected immediately to the external surface and further connected between the external surface and the first optical surface. A boundary line of the second and the first optical surfaces is not disposed at the external surface. The third optical surface and the external surface are immediately connected. Accordingly, local uniformity of light distribution of the optical lens is improved.Type: GrantFiled: June 15, 2016Date of Patent: September 19, 2017Assignee: KAISTAR LIGHTING (XIAMEN) CO., LTD.Inventors: Sheng-Lung Tsai, Jenn-Yuan Hsu, Hsin-Yu Chiang, Hsin-Ming Chiang
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Publication number: 20170108738Abstract: A direct-lit type backlight source includes a backplate and a point light source array disposed on the backplate. A light output shape of a first optical lens employed by each of point light sources of corner regions of the point light source array and that of a second optical lens employed by each of a plurality of point light sources of the non-corner region are different. For instance, the light output shape of the first optical lens is symmetrical in a first direction and asymmetrical in a vertical second direction. Moreover, a liquid crystal television adopting the direct-lit type backlight source is provided. The light-output shape of the optical lens adopted by each of the point light sources of the respective corners is designed to illuminate the corners uncovered by light source in the prior art, which can improve optical uniformity of the corners.Type: ApplicationFiled: December 25, 2016Publication date: April 20, 2017Inventors: Jenn-Yuan Hsu, Sheng-Lung Tsai, Hsin-Yu Chiang
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Publication number: 20160290595Abstract: A LED lamp and an optical lens thereof are provided. The LED lamp includes a LED light source and an optical lens covering the LED light source. The optical lens includes a dome structure and a protrusion structure. The dome structure has an external surface. The protrusion structure is disposed protruding from the external surface and includes oppositely-disposed first and second side surfaces. The first side surface includes first and second optical surfaces. The second side surface includes a third optical surface. The second optical surface is connected immediately to the external surface and further connected between the external surface and the first optical surface. A boundary line of the second and the first optical surfaces is not disposed at the external surface. The third optical surface and the external surface are immediately connected. Accordingly, local uniformity of light distribution of the optical lens is improved.Type: ApplicationFiled: June 15, 2016Publication date: October 6, 2016Inventors: Sheng-Lung Tsai, Jenn-Yuan Hsu, Hsin-Yu Chiang, Hsin-Ming Chiang