Patents by Inventor Hsiu-Ting Chen
Hsiu-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Patent number: 11916091Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.Type: GrantFiled: April 15, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
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Publication number: 20220238656Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
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Patent number: 11302782Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.Type: GrantFiled: May 4, 2020Date of Patent: April 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
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Publication number: 20200266274Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
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Patent number: 10644116Abstract: A method includes forming a recess in a semiconductor substrate, the recess being adjacent to a gate stack, performing an epitaxial growth process within the recess to form a straining region, and forming a defect within the straining region in-situ with the epitaxial growth process.Type: GrantFiled: February 6, 2014Date of Patent: May 5, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
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Patent number: 10068774Abstract: A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1?xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1?yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1?zGez is formed on the second epitaxial layer. Z is smaller than y.Type: GrantFiled: December 1, 2017Date of Patent: September 4, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Min Huang, Hsiu-Ting Chen, Shih-Chieh Chang
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Patent number: 10008383Abstract: The present disclosure provides a semiconductor structure includes a substrate and an epitaxy region that is partially disposed in the substrate. A doping concentration of the epitaxy region increases from a bottom portion to a top portion of the epitaxy region. The present disclosure also provides a method for manufacturing the semiconductor structure, including forming a recess in a substrate; forming an epitaxy region in the recess; and in situ doping the epitaxy region to form a doping concentration profile increasing from a bottom portion to a top portion of the epitaxy region.Type: GrantFiled: March 10, 2014Date of Patent: June 26, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Ming Huang, Hsiu-Ting Chen, Shih-Chieh Chang
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Publication number: 20180090330Abstract: A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1?xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1?yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1?zGez is formed on the second epitaxial layer. Z is smaller than y.Type: ApplicationFiled: December 1, 2017Publication date: March 29, 2018Inventors: Yi-Min HUANG, Hsiu-Ting CHEN, Shih-Chieh CHANG
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Publication number: 20180033630Abstract: A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1-xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1-yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1-zGez is formed on the second epitaxial layer. Z is smaller than y.Type: ApplicationFiled: July 28, 2016Publication date: February 1, 2018Inventors: Yi-Min HUANG, Hsiu-Ting CHEN, Shih-Chieh CHANG
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Patent number: 9870926Abstract: A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1-xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1-yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1-zGez is formed on the second epitaxial layer. Z is smaller than y.Type: GrantFiled: July 28, 2016Date of Patent: January 16, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Min Huang, Hsiu-Ting Chen, Shih-Chieh Chang
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Patent number: 9698249Abstract: The present disclosure provides a semiconductor structure having an insulating layer positioning on a substrate; a semiconductor fin partially located in the insulating layer; and a metal gate over the semiconductor fin and the insulating layer. The semiconductor fin includes a first region including a first lattice constant and a second region in proximity to the metal gate, including a second lattice constant. At least one dislocation is located only in the second region of the semiconductor fin. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a gate over a first semiconductor layer, removing a portion of the first semiconductor layer in proximity to a sidewall of the gate and obtaining a recess, and forming a second semiconductor layer in the recess. At least one dislocation is in-situ formed in the second semiconductor layer without extending to the first semiconductor layer.Type: GrantFiled: January 17, 2014Date of Patent: July 4, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Ming Huang, Hsiu-Ting Chen, Shih-Chieh Chang
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Patent number: 9614085Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.Type: GrantFiled: August 29, 2016Date of Patent: April 4, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-I Liao, Shih-Chieh Chang, Hsiu-Ting Chen, Shih-Hsien Cheng
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Patent number: 9543387Abstract: A semiconductor device includes a gate structure located on a substrate and a raised source/drain region adjacent to the gate structure. The raised source/drain region includes: a first epitaxial-grown doped layer of the raised source/drain region in contact with the substrate; a second epitaxial-grown doped layer on the first epitaxial-grown doped layer and including a same dopant species as the first epitaxial-grown doped layer, wherein the second epitaxial-grown doped layer includes a higher dopant concentration than the first epitaxial-grown doped layer and interfacing the gate structure by using a predetermined distance; and a third epitaxial-grown doped layer on the second epitaxial-grown doped layer and including the same dopant species as the first epitaxial-grown doped layer, wherein the third epitaxial-grown doped layer includes a higher dopant concentration than the second epitaxial-grown doped layer.Type: GrantFiled: March 10, 2014Date of Patent: January 10, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Chieh Chang, Ying-Min Chou, Yi-Ming Huang, Wen-Chu Hsiao, Hsiu-Ting Chen, Huai-Tei Yang
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Publication number: 20160365448Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.Type: ApplicationFiled: August 29, 2016Publication date: December 15, 2016Inventors: CHIN-I LIAO, SHIH-CHIEH CHANG, HSIU-TING CHEN, SHIH-HSIEN CHENG
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Publication number: 20160293701Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.Type: ApplicationFiled: March 31, 2015Publication date: October 6, 2016Inventors: CHIN-I LIAO, SHIH-CHIEH CHANG, HSIU-TING CHEN, SHIH-HSIEN CHENG
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Patent number: 9450047Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.Type: GrantFiled: March 31, 2015Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-I Liao, Shih-Chieh Chang, Hsiu-Ting Chen, Shih-Hsien Cheng
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Publication number: 20150255578Abstract: A semiconductor device includes a gate structure located on a substrate and a raised source/drain region adjacent to the gate structure. The raised source/drain region includes: a first epitaxial-grown doped layer of the raised source/drain region in contact with the substrate; a second epitaxial-grown doped layer on the first epitaxial-grown doped layer and including a same dopant species as the first epitaxial-grown doped layer, wherein the second epitaxial-grown doped layer includes a higher dopant concentration than the first epitaxial-grown doped layer and interfacing the gate structure by using a predetermined distance; and a third epitaxial-grown doped layer on the second epitaxial-grown doped layer and including the same dopant species as the first epitaxial-grown doped layer, wherein the third epitaxial-grown doped layer includes a higher dopant concentration than the second epitaxial-grown doped layer.Type: ApplicationFiled: March 10, 2014Publication date: September 10, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: SHIH-CHIEH CHANG, YING-MIN CHOU, YI-MING HUANG, WEN-CHU HSIAO, HSIU-TING CHEN, HUAI-TEI YANG
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Publication number: 20150255601Abstract: The present disclosure provides a semiconductor structure includes a substrate and an epitaxy region that is partially disposed in the substrate. A doping concentration of the epitaxy region increases from a bottom portion to a top portion of the epitaxy region. The present disclosure also provides a method for manufacturing the semiconductor structure, including forming a recess in a substrate; forming an epitaxy region in the recess; and in situ doping the epitaxy region to form a doping concentration profile increasing from a bottom portion to a top portion of the epitaxy region.Type: ApplicationFiled: March 10, 2014Publication date: September 10, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: YI-MING HUANG, HSIU-TING CHEN, SHIH-CHIEH CHANG
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Publication number: 20150221509Abstract: A method includes forming a recess in a semiconductor substrate, the recess being adjacent to a gate stack, performing an epitaxial growth process within the recess to form a straining region, and forming a defect within the straining region in-situ with the epitaxial growth process.Type: ApplicationFiled: February 6, 2014Publication date: August 6, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng