Patents by Inventor Hsuan Chang

Hsuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085369
    Abstract: Disclosed is a self-powered formaldehyde sensing device, comprising: a triboelectric material electrode layer including a first substrate and a first electrode layer formed on the first substrate; a triboelectric material dielectric layer including a second substrate, a second electrode layer formed on the second substrate, a dielectric reacting layer formed on the second electrode layer, and a reaction modification layer formed on the dielectric reacting layer to surface-modify the dielectric reacting layer, the reaction modification layer being a phosphomolybdic acid complex (cPMA) layer, the phosphomolybdic acid complex of the phosphomolybdic acid complex layer being obtained by dissolving 4,4?-bipyridine (BPY) in isopropanol (IPA) and then mixing with phosphomolybdic acid (PMA) solution; an elastic spacer; and an external circuit.
    Type: Application
    Filed: December 21, 2022
    Publication date: March 14, 2024
    Applicant: National Taiwan University of Science and Technology
    Inventors: Chih-Yu Chang, Chun-Yi Ho, Yu-Hsuan Cheng, Ying-Ying Chen
  • Publication number: 20240086633
    Abstract: A method for generating and outputting a message is implemented using an electronic device the stores a computer program product and a text database. The text database includes a main message template, a template text that includes a placeholder, and a word group that includes a plurality of preset words for replacing the placeholder. The method includes: in response to receipt of a command for execution of the computer program product, displaying an editing interface including the main message template; in response to receipt of user operation of a selection of the main message template, displaying the template text; in response to receipt of user operation of a selection of one of the preset words via the user interface, generating an edited text by replacing the placeholder with the one of the preset words in the template text; and outputting the edited text as a message.
    Type: Application
    Filed: April 25, 2023
    Publication date: March 14, 2024
    Inventors: Yi-Ru CHIU, Ting-Yi LI, Hong-Xun WANG, Jin-Lin CHEN, Chih-Hsuan YEH, Chia-Chi YIN, Wei-Ting LI, Po-Lun CHANG
  • Publication number: 20240088307
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240079524
    Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN
  • Patent number: 11923250
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Publication number: 20240071981
    Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
  • Publication number: 20240067746
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 29, 2024
    Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
  • Patent number: 11915980
    Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Yi Tsai, Yi-Hsuan Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Publication number: 20240047959
    Abstract: A power circuit, adapted to supply power to a computer system, includes a power connector, a charge unit, a short current protection circuit, and a first switch circuit. The power connector is configured to connect to the adapter to receive an input voltage. The charge unit includes an input end configured to receive the input voltage and an output end. The charge unit converts the input voltage into a system voltage. The short current protection circuit includes a detection circuit and a first logic control circuit. The detection circuit detects an impedance of at least one of the input end and the output end to generate a detection signal. The first logic control circuit generates a power control signal according to the detection signal. The first switch circuit is connected between the power connector and the input end and is controlled by the power control signal.
    Type: Application
    Filed: January 24, 2023
    Publication date: February 8, 2024
    Inventor: Hua-Hsuan CHANG
  • Publication number: 20240038684
    Abstract: A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 1, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Ming-Hua Tsai, Hao Ping Yan, Chin-Chia Kuo, Wei Hsuan Chang
  • Publication number: 20240010971
    Abstract: Disclosed herein are spore compositions and methods of producing such compositions. Additionally disclosed herein are plant protection products benefiting from such spore compositions and methods of using such compositions for the benefit of plants, for the reduction of pathogen emissions to nearby areas and for the benefit of animals or humans. Further disclosed herein are methods of efficient fermentation.
    Type: Application
    Filed: December 10, 2021
    Publication date: January 11, 2024
    Inventors: Tobias MAY, Reinhard STIERL, Hsuan CHANG, Daniel Christoph HEINRICH, Evangelina Priya HAAS, Andrea HEROLD
  • Patent number: 11866485
    Abstract: The present disclosure relates to an antibody or antigen-binding fragment thereof that specifically binds to a spike protein of SARS-CoV-2. The present disclosure also relates to a pharmaceutical composition, a method for treating and/or preventing diseases and/or disorders caused by a coronavirus in a subject in need thereof, and a method for detecting a coronavirus in a sample.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: January 9, 2024
    Assignee: ACADEMIA SINICA
    Inventors: Kuo-I Lin, Che Ma, Chi-Huey Wong, Szu-Wen Wang, Yi-Hsuan Chang, Xiaorui Chen, Han-Yi Huang
  • Patent number: 11859663
    Abstract: A linear guideway, a sliding module thereof, and a circulation seat thereof are provided. The circulation seat has an inherently one-piece structure, which includes two turning portions, a middle retaining portion, and two lateral retaining portions. The middle retaining portion has a two-stepped structure, which includes a connection bar and a limiting bar that is connected to the connection bar. The connection bar is connected to and arranged between the two turning portions, and a distance between two long lateral surfaces of the connection bar gradually increases along a direction away from the limiting bar. The two lateral retaining portions are connected to and arranged between the two turning portions, and the two lateral retaining portions are respectively located at two opposite sides of the middle retaining portion.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: January 2, 2024
    Assignee: OME TECHNOLOGY CO., LTD.
    Inventors: Kuo-Fu Liao, Wen-Bin Wu, Jo-Hsuan Chang, Wei-Min Wang, Jhih-Jie Luo
  • Patent number: 11847080
    Abstract: An all-in-one computer includes a display, a Universal Serial Bus (USB) Type-C port, a plurality of USB Type-A ports, a USB hub, a demultiplexer, and a Power Delivery (PD) controller. The USB hub is coupled to the plurality of USB Type-A ports. The demultiplexer is coupled between the display, the USB Type-C port, and the USB hub. The PD controller is to control the demultiplexer and the USB hub to pass a display signal input to the USB Type-C port to the display and pass signals input to the USB hub from the plurality of USB Type-A ports to the USB Type-C port with a computing device coupled to the USB Type-C port.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 19, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jui-Hsuan Chang, Chia-Ching Lu, Shih-Chieh Liu, Nam Hoang Nguyen
  • Publication number: 20230393242
    Abstract: A system and method for estimating free space and assigning free space probabilities in point cloud data associated with an autonomous vehicle traveling on a surface, including taking into account sensor noise, sensor availability, obstacle heights, and distance of obstacles from the sensor. System and method can include determining surface planes and classifying point cloud points according to whether or not the points fall on surface planes, among other factors.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 7, 2023
    Inventors: Abhishek Ravi, Gregory J. Buitkus, Sai Ravi Teja Boggavarapu, Raajitha Gummadi, Derek Kane, Yu-Hsuan Chang
  • Patent number: 11838165
    Abstract: A method used for controlling a wireless communication system includes receiving a packet, demodulating the packet to obtain a first channel characteristic index and a second channel characteristic index of the wireless communication system, selecting a length of a guard interval according to the first channel characteristic index, and selecting a length of a long training field according to the second channel characteristic index. When signal quality corresponding to the packet is higher, the length of the guard interval is shorter, and the length of the long training field is shorter.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: December 5, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wei-Hsuan Chang, Chien-Hsun Liao
  • Publication number: 20230387994
    Abstract: A method includes receiving CSI frames among P CSI frames transmitted from another electronic device. The method includes estimating a CSI from each of the received CSI frames as an available CSI estimate. The method includes identifying an impairment model accounting for inclusion of amplitude or phase errors of an estimated CSI corresponding to a p-th CSI frame among the P CSI frames. The method includes compensating, via the impairment model, for the errors in amplitude and phase of P CSI estimates. Compensating for the errors in amplitude and phase of the P CSI estimates can be based on: approximating a missing CSI estimate based on the available CSI estimates; determining an AGC gain value; or computing the errors in the phase based on a weighted least-squares solution. The method includes estimating a breathing rate of a subject based on different spatial dimensions of the P compensated CSI estimates.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 30, 2023
    Inventors: Vishnu Vardhan Ratnam, Hao Chen, Abhishek Sehgal, Hao-Hsuan Chang
  • Publication number: 20230370921
    Abstract: Various solutions for reducing inter-radio access technology (inter-RAT) measurements for reduced capability (RedCap) user equipment (UE) with respect to UE and network apparatus in mobile communications are described. An apparatus may receive a neighbor cell information from a first RAT. The apparatus may determine whether a neighbor cell of the neighbor cell information supports RedCap UE. The apparatus may perform a measurement on the neighbor cell in an event that the neighbor cell supports the RedCap UE. The apparatus may skip the measurement on the neighbor cell in an event that the neighbor cell does not support the RedCap UE.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 16, 2023
    Inventors: Yun-Hsuan Chang, Chun-Pin Chen
  • Patent number: 11817782
    Abstract: An inverter device includes a converter circuit and a filter. The converter circuit converts a DC input voltage into an AC intermediate voltage based on six control signals, and includes first and second converters. Each of the first and second converters includes three switches, two diodes and a coupled inductor circuit. The switches of the first converter operate respectively based on three of the control signals. The switches of the second converter operate respectively based on the other three of the control signals. The filter filters the AC intermediate voltage to generate an AC output voltage.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: November 14, 2023
    Assignee: I SHOU UNIVERSITY
    Inventors: Chien-Hsuan Chang, Yi-Fan Chen
  • Publication number: 20230360728
    Abstract: A beta2-microglobulin concentration analyzing method includes: inputting samples that are prepared from spent dialysate and corresponding to sampling time points into a differential mobility analyzing device for analysis to obtain beta2-microglobulin concentrations, multiplying the sampling time points with a dialysate flowrate respectively to obtain spent dialysate volumes, performing fitting on the beta2-microglobulin concentrations to obtain a concentration-spent dialysate volume fitting curve, and performing integration on the concentration-spent dialysate volume fitting curve to generate a total dialyzed weight.
    Type: Application
    Filed: April 7, 2023
    Publication date: November 9, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ching-Hsuan CHANG, Fang-Hsin LIN, Kuan-Hung LIU, Bin HSU