Patents by Inventor Hsueh-Chih Yang
Hsueh-Chih Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240028451Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.Type: ApplicationFiled: August 4, 2023Publication date: January 25, 2024Inventors: Hiroki NOGUCHI, Yu-Der CHIH, Hsueh-Chih YANG, Randy OSBORNE, Win San KHWA
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Patent number: 11762732Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.Type: GrantFiled: December 20, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hiroki Noguchi, Yu-Der Chih, Hsueh-Chih Yang, Randy Osborne, Win San Khwa
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Patent number: 11714717Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.Type: GrantFiled: March 24, 2022Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Chia-Fu Lee, Chien-Yin Liu, Yi-Chun Shih, Kuan-Chun Chen, Hsueh-Chih Yang, Shih-Lien Linus Lu
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Publication number: 20230236929Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.Type: ApplicationFiled: March 14, 2023Publication date: July 27, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
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Patent number: 11609815Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.Type: GrantFiled: August 30, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun Lin, Pei-Ling Tseng, Hsueh-Chih Yang, Chung-Cheng Chou, Yu-Der Chih
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Publication number: 20230063758Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
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Patent number: 11556414Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.Type: GrantFiled: April 5, 2021Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Yin Liu, Yu-Der Chih, Hsueh-Chih Yang, Jonathan Tehan Chen, Kuan-Chun Chen
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Publication number: 20220214943Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.Type: ApplicationFiled: March 24, 2022Publication date: July 7, 2022Inventors: Yu-Der CHIH, Chia-Fu LEE, Chien-Yin LIU, Yi-Chun SHIH, Kuan-Chun CHEN, Hsueh-Chih YANG, Shih-Lien Linus LU
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Publication number: 20220114046Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Hiroki Noguchi, Yu-Der Chih, Hsueh-Chih Yang, Randy Osborne, Win-San Khwa
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Patent number: 11294764Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.Type: GrantFiled: February 10, 2020Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Chia-Fu Lee, Chien-Yin Liu, Yi-Chun Shih, Kuan-Chun Chen, Hsueh-Chih Yang, Shih-Lien Linus Lu
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Patent number: 11204826Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.Type: GrantFiled: August 8, 2019Date of Patent: December 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hiroki Noguchi, Yu-Der Chih, Hsueh-Chih Yang, Randy Osborne, Win San Khwa
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Publication number: 20210224154Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Chien-Yin LIU, Yu-Der CHIH, Hsueh-Chih YANG, Jonathan Tehan CHEN, Kuan-Chun CHEN
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Patent number: 10970167Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.Type: GrantFiled: January 15, 2020Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Yin Liu, Yu-Der Chih, Hsueh-Chih Yang, Jonathan Tehan Chen, Kuan-Chun Chen
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Publication number: 20200174883Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.Type: ApplicationFiled: February 10, 2020Publication date: June 4, 2020Inventors: Yu-Der CHIH, Chia-Fu LEE, Chien-Yin LIU, Yi-Chun SHIH, Kuan-Chun CHEN, Hsueh-Chih YANG, Shih-Lien Linus LU
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Publication number: 20200151057Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Chien-Yin Liu, Yu-Der Chih, Hsueh-Chih Yang, Jonathan Tehan Chen, Kuan-Chun Chen
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Publication number: 20200104205Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.Type: ApplicationFiled: August 8, 2019Publication date: April 2, 2020Inventors: Hiroki Noguchi, Yu-Der Chih, Hsueh-Chih Yang, Randy Osborne, Win San Khwa
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Patent number: 10599517Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.Type: GrantFiled: April 28, 2018Date of Patent: March 24, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Yin Liu, Yu-Der Chih, Hsueh-Chih Yang, Jonathan Tehan Chen, Kuan-Chun Chen
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Patent number: 10558525Abstract: A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.Type: GrantFiled: June 27, 2017Date of Patent: February 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Chia-Fu Lee, Chien-Yin Liu, Yi-Chun Shih, Kuan-Chun Chen, Hsueh-Chih Yang, Shih-Lien Linus Lu
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Patent number: 10180877Abstract: The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream.Type: GrantFiled: May 12, 2016Date of Patent: January 15, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Yin Liu, Hsueh-Chih Yang, Kuan-Chun Chen, Yue-Der Chih, Yi-Chun Shih
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Publication number: 20180004602Abstract: A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.Type: ApplicationFiled: June 27, 2017Publication date: January 4, 2018Inventors: Yu-Der CHIH, Chia-Fu LEE, Chien-Yin LIU, Yi-Chun SHIH, Kuan-Chun CHEN, Hsueh-Chih YANG, Shih-Lien Linus LU