Patents by Inventor Hsuen-Wei Chen

Hsuen-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Highly scalable single-poly non-volatile memory cell
    Patent number: 9640262
    Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: May 2, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Chun-Hsiao Li, Hsuen-Wei Chen
  • Nonvolatile memory structure
    Patent number: 9391083
    Abstract: A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 12, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Wei-Ren Chen, Hsuen-Wei Chen, Mu-Ying Tsao, Ying-Je Chen
  • HIGHLY SCALABLE SINGLE-POLY NON-VOLATILE MEMORY CELL
    Publication number: 20160013199
    Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.
    Type: Application
    Filed: May 22, 2015
    Publication date: January 14, 2016
    Inventors: Te-Hsun Hsu, Chun-Hsiao Li, Hsuen-Wei Chen
  • NONVOLATILE MEMORY STRUCTURE
    Publication number: 20150091074
    Abstract: A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.
    Type: Application
    Filed: September 4, 2014
    Publication date: April 2, 2015
    Inventors: Te-Hsun Hsu, Wei-Ren Chen, Hsuen-Wei Chen, Mu-Ying Tsao, Ying-Je Chen