Patents by Inventor Huai-Shih Hsu

Huai-Shih Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synchronized two-level graphics processing cache
    Patent number: 7205994
    Abstract: A synchronized two-level cache including a level 1 cache and a level 2 cache is implemented in a graphics processing system. The level 2 cache is further partitioned into a number of slots which are dynamically allocated to texture maps as needed. The reference counter of each of the cache lines in each cache level is tracked so that a cache line is not overwritten with new data prior to transferring old data out to the recipient device. The age status of each cache line is tracked so that the oldest cache line is overwritten first. The use of a synchronized two-level cache system conserves system memory bandwidth and reduces memory latency, thereby improving the graphics processing system's performance.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: April 17, 2007
    Assignee: S3 Graphics Co., Ltd.
    Inventors: Chih-Hong Fu, I-Chung Ling, Huai-Shih Hsu
  • Synchronized two-level graphics processing cache
    Publication number: 20050179693
    Abstract: A synchronized two-level cache including a level 1 cache and a level 2 cache is implemented in a graphics processing system. The level 2 cache is further partitioned into a number of slots which are dynamically allocated to texture maps as needed. The reference counter of each of the cache lines in each cache level is tracked so that a cache line is not overwritten with new data prior to transferring old data out the to recipient device. The age status of each cache line is tracked so that the oldest cache line is overwritten first. The use of a synchronized two-level cache system conserves system memory bandwidth and reduces memory latency, thereby improving the graphics processing system's performance.
    Type: Application
    Filed: October 18, 2004
    Publication date: August 18, 2005
    Inventors: Chih-Hong Fu, I-Chung Ling, Huai-Shih Hsu
  • Synchronized two-level graphics processing cache
    Patent number: 6825848
    Abstract: A synchronized two-level cache including a Level 1 cache and a Level 2 cache is implemented in a graphics processing system. The Level 2 cache is further partitioned into a number of slots which are dynamically allocated to texture maps as needed. The reference counter of each of the cache lines in each cache level is tracked so that a cache line is not overwritten with new data prior to transferring old data out to the recipient device. The age status of each cache line is tracked so that the oldest cache line is overwritten first. The use of synchronized two-level cache system conserves system memory bandwidth and reduces memory latency, thereby improving the graphics processing system's performance.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: November 30, 2004
    Assignee: S3 Graphics Co., Ltd.
    Inventors: Chih-Hong Fu, I-Chung Ling, Huai-Shih Hsu