Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. A first width direction of the first conductive contact structure is substantially parallel to a second width direction of the first conductive via structure.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.

Abstract: Embodiments described herein provide systems and methods for training a sequential recommendation model. Methods include determining a difficulty and quality (DQ) score associated with user behavior sequences from a training dataset. User behavior sequences are sampled during training based on their DQ scores. A meta-extrapolator may also be trained based on user behavior sequences sampled according to DQ score. The meta-extrapolator may be trained with high quality low difficulty sequences. The meta-extrapolator may then be used with an input of high quality high difficulty sequences to generate synthetic user behavior sequences. The synthetic user behavior sequences may be used to augment the training dataset to fine-tune the sequential recommendation model, while continuing to sample user behavior sequences based on DQ score. As the DQ score is based on current model predictions, DQ scores iteratively update during the training process.

Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.

Abstract: A tamper-evident container including: a container body having a first hollow convex loop on a periphery of an opening thereof; and a lid having a second hollow convex loop and a force application structure, where the second hollow convex loop is used to engage with the first hollow convex loop, and a loop-shaped breakable line is provided on a loop-shaped top surface of the second hollow convex loop; where, when an illegitimate user applies a lifting force on any local area of the second hollow convex loop of the lid to make the local area moving upward with a displacement exceeding a threshold, a corresponding local area of the loop-shaped breakable line will be broken to show that the tamper-evident container has been tampered with.

Abstract: A self-moving robot and a method of automatically determining an accessible region are provided. The self-moving robot performs a setting process of 2D obstacles to generate a goal map based on an exploration map, performs a setting process of 3D obstacles on the goal map to update the accessible region of the goal map when a 3D obstacle is detected, performs an avoidance action, and, moves within the accessible region of the goal map. The disclosure prevents the self-moving robot from colliding with obstacles or being trapped.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises an insulating structure, a dielectric structure, a metal structure, a conductive spacer and a dielectric spacer. The dielectric structure is formed on the insulating structure. The metal structure is formed on and surrounded by the dielectric structure. A bottom surface and a lateral surface of the metal structure are in direct contact with the dielectric structure. The conductive spacer is formed on the insulating structure. The conductive spacer surrounds the dielectric structure. The dielectric spacer is formed on the insulating structure, wherein the dielectric spacer surrounds the conductive spacer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments between the pair of source/drain regions; and a protection structure overlapping the gate electrode.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: A feature identifying method and an electronic device are provided. The method includes: obtaining a plurality of physiological information obtained by measuring a subject at a plurality of time points in one day; converting the plurality of physiological information into a plurality of correlation features respectively; establishing a plurality of first risk prediction models according to the plurality of correlation features, and identifying at least one first correlation feature from the plurality of correlation features according to the plurality of first risk prediction models; establishing a plurality of second risk prediction models according to the at least one first correlation feature, and identifying, according to the plurality of second risk prediction models, at least one second correlation feature capable of predicting a specific disease from the at least one first correlation feature; and outputting the at least one second correlation feature.

Abstract: The present disclosure discloses a container positioning method and apparatus based on multi-line laser data fusion, the method comprising: acquiring point cloud data of at least two multi-line laser radars, and performing point cloud data fusion according to a coordinate system relationship between the at least two laser radars; performing clustering of scanning lines according to the fused point cloud data, and acquiring an edge point of a top surface or a side surface of a target container according to the clustered scanning lines; acquiring a contour of the top surface or the side surface of the target container according to the edge point of the top surface or the side surface of the target container to determine a central point and a heading angle of the target container so as to determine a position of the target container.

Abstract: A sensing module including an illumination device and a sensing device is disclosed. The illumination device is configured to provide an illumination beam or sequentially provide multiple sub-beams having directivity to a sensing area respectively, and the sensing area includes multiple different sub-sensing areas. The sensing device is configured to receive multiple reflected beams from the sub-sensing areas to respectively obtain multiple sub-depth signals, and generate a depth signal according to the sub-depth signals.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Abstract: A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a base layer, a magnetic shielding layer disposed on the base layer, a carrier layer disposed on the magnetic shielding layer, a receiver disposed on the carrier layer, a storage layer disposed between the base layer and the magnetic shielding layer, and a magnetic shielding element disposed on the carrier layer and surrounding the receiver.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments extending in parallel along the first direction; and a protection structure over the substrate and at least partially overlaps the gate electrode.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.