Abstract: Some implementations herein include a detection circuit and a fast and accurate in-line method for detecting blockage on a droplet generator head of an extreme ultraviolet exposure tool without impacting the flow of droplets of a target material through the droplet generator head. In some implementations described herein, the detection circuit includes a switch circuit that is configured in an open configuration, in which the switch is electrically open between two electrode elements. When an accumulation of the target material occurs across two or more electrode elements on the droplet generator head, the accumulation functions as a switch that closes the detection circuit. A controller may detect closure of the detection circuit.

Abstract: A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.

Abstract: Techniques for managing threads involve acquiring respective runtime addresses and call information of a plurality of lock objects in a plurality of threads, and determining, from the plurality of lock objects, a first group of lock objects associated with first call information and a second group of lock objects associated with second call information different from the first call information. The techniques further involve providing an indication that a deadlock exists in the plurality of threads if it is determined that a first group of runtime addresses of the first group of lock objects overlaps with a second group of runtime addresses of the second group of lock objects. Accordingly, potential deadlocks in a plurality of threads can be analyzed, thereby avoiding the inability of the threads to proceed normally due to the deadlocks.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: A method includes moving a wafer stage to a first station on a table body of a lithography chamber; placing a wafer on a top surface of the wafer stage; emitting a first laser beam from a first laser emitter toward a first beam splitter on a first sidewall of the wafer stage, wherein a first portion of the first laser beam is reflected by the first beam splitter to form a first reflected laser beam, and a second portion of the first laser beam transmits through the first beam splitter to form a first transmitted laser beam; calculating a position of the wafer stage on a first axis based on the first reflected laser beam; after calculating the position of the wafer, moving the wafer stage to a second station on the table body; and performing a lithography process to the wafer.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: An extreme ultraviolet (EUV) photolithography system generates EUV light by irradiating droplets with a laser. The system includes a droplet generator with a nozzle and a piezoelectric structure coupled to the nozzle. The generator outputs groups of droplets. A control system applies a voltage waveform to the piezoelectric structure while the nozzle outputs the group of droplets. The waveform causes the droplets of the group to have a spread of velocities that results in the droplets coalescing into a single droplet prior to being irradiated by the laser.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Abstract: A polyurethane composition is provided. The polyurethane composition comprises (A) a polyurethane-prepolymer prepared by reacting at least one polyisocyanate compound with a first polyol component; and (B) a second polyol component; wherein at least one of the first polyol component and the second polyol component comprises an ester/ether random copolymer polyol synthesized by reacting a starting material polyether polyol with at least one monomeric polyhydric alcohol and at least one monomeric multifunctional carboxylic acid or anhydride thereof. The polyurethane foam prepared by using the polyurethane composition can achieve inhibited internal heat buildup, high thermal stability, superior tear strength, enhanced abrasion resistance and good hydrolysis resistance. A polyurethane product prepared with said foam, a method for preparing the polyurethane foam and a method for improving the performance property of the polyurethane foam are also provided.

Abstract: The present disclosure provides a neural network-based visual detection and tracking method of an inspection robot, which includes the following steps of: 1) acquiring environmental images of a dynamic background a movement process of the robot; 2) preprocessing the acquired images; 3) detecting human targets and specific behaviors in the images in the robot body, and saving the sizes, position information and features of the human targets with the specific behaviors; 4) controlling the orientation of a robot gimbal by using a target tracking algorithm to make sure that a specific target is always located at the central positions of the images; and 5) controlling the robot to move along with a tracked object. The neural network-based visual detection and tracking method of an inspection robot in the present disclosure has a quite high adaptive ability, achieves better detection and tracking effects on targets in a dynamic background scene.

Abstract: Embodiments of the present disclosure provide a method and device for deduplication. Specifically, the method may comprise obtaining a property of a file stream, the property of a file stream including a file type or a magic number identifying a format of a protocol or a file. The method further includes in response to receiving an I/O request for a data block of the file stream, assigning a deduplication level to the I/O request based on the property of the file stream. Moreover, the method further includes deduplicating the data block of the file stream based on the deduplication level assigned to the I/O request. In addition, a corresponding device and computer program product are provided.

Abstract: A method for using an extreme ultraviolet radiation source is provided. The method includes assembling a first droplet generator onto a port of a vessel; ejecting a target droplet from the first droplet generator to a zone of excitation in front of a collector; emitting a laser toward the zone of excitation, such that the target droplet is heated by the laser to generate extreme ultraviolet (EUV) radiation; stopping the ejection of the target droplet; after stopping the ejection of the target droplet, disassembling the first droplet generator from the port of the vessel; after disassembling the first droplet generator from the port of the vessel, inserting a cleaning device into the vessel through the port; and cleaning the collector by using the cleaning device.

Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become energized and emit extreme ultraviolet radiation. A collector reflects the extreme ultraviolet radiation toward a photolithography target. The photolithography system isolates a source of droplets from oxidants to prevent the oxidation of the nozzle or the formation of metal oxides on the nozzle, both of which can adversely affect an ability of the nozzle to generate a sufficient amount of droplets and/or direct the droplets in a desired direction.

Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

Abstract: A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a base layer, a magnetic shielding layer disposed on the base layer, a carrier layer disposed on the magnetic shielding layer, and a receiver disposed on the carrier layer. The receiver is configured to receive a microwave signal from a signal source electrically isolated from the receiver, and the microwave signal is used for controlling the movement of the semiconductor substrate stage.

Abstract: A photolithographic apparatus includes a droplet generator, a droplet generator maintenance system, and a controller communicating with the droplet generator maintenance system. The droplet generator maintenance system operatively communicates with the droplet generator, a coolant distribution unit, a gas supply unit, and a supporting member. The gas supply unit includes a heat exchange assembly and an air heating assembly. The coolant distribution unit is configured to control the temperature of the droplet generator within the acceptable droplet generator range.

Abstract: A chip package structure is provided. The chip package structure includes a first wiring substrate including a substrate, a first pad, a second pad, and an insulating layer. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer includes tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad. The chip package structure includes a chip over the second surface of the substrate. The chip package structure includes a conductive bump between the second pad and the chip.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

Abstract: A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.