Patents by Inventor Huan-Just Lin

Huan-Just Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190341263
    Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Publication number: 20190333820
    Abstract: A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Yun-Min Chang, Chien-An Chen, Guan-Ren Wang, Peng Wang, Huang-Ming Chen, Huan-Just Lin
  • Patent number: 10461170
    Abstract: A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Patent number: 10418271
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Cheng-Tung Lin, Chih-Tang Peng, Chien-Hsun Wang, Bing-Hung Chen, Huan-Just Lin, Yung-Cheng Lu
  • Publication number: 20190259613
    Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Huan-Just Lin, Huang-Ming Chen, Yang-Cheng Wu, Cheng-Hua Yang
  • Patent number: 10388531
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Patent number: 10325994
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
  • Patent number: 10312089
    Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Huan-Just Lin, Huang-Ming Chen, Yang-Cheng Wu, Cheng-Hua Yang
  • Publication number: 20190164759
    Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
    Type: Application
    Filed: March 16, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien HUANG, Tsai-Chun LI, Huan-Just LIN, Huang-Ming CHEN, Yang-Cheng WU, Cheng-Hua YANG
  • Patent number: 10276725
    Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, De-Fang Chen, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Publication number: 20190122936
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 10163723
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20180350655
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Teng-Chun TSAI, Bing-Hung CHEN, Chien-Hsun WANG, Cheng-Tung LIN, Chih-Tang PENG, De-Fang CHEN, Huan-Just LIN, Li-Ting WANG, Yung-Cheng LU
  • Publication number: 20180240882
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 23, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang PENG, Tai-Chun HUANG, Teng-Chun TSAI, Cheng-Tung LIN, De-Fang CHEN, Li-Ting WANG, Chien-Hsun WANG, Huan-Just LIN, Yung-Cheng LU, Tze-Liang LEE
  • Patent number: 10026658
    Abstract: Systems and methods are provided for fabricating nanowire devices on a substrate. A first nanowire and a second nanowire are formed on a substrate, the first nanowire and the second nanowire extending substantially vertically relative to the substrate. A first source region and a first drain region are formed with n-type dopants, the first nanowire being disposed between the first source region and the first drain region. A second source region and a second drain region are formed with p-type dopants, the second nanowire being disposed between the second source region and the second drain region.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, De-Fang Chen, Huan-Just Lin
  • Publication number: 20180151382
    Abstract: To pattern a gate electrode, a mandrel of material is initially deposited and then patterned. In an embodiment the patterning is performed by performing a first etching process and to obtain a rough target and then to perform a second etching process with different etch parameters to obtain a precise target. The mandrel is then used to form spacers which can then be used to form masks to pattern the gate electrode.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 31, 2018
    Inventors: Chi-Kang Liu, Jr-Jung Lin, Huan-Just Lin, Ming-Hsi Yeh, Sung-Hsun Wu
  • Patent number: 9978850
    Abstract: An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Huan-Just Lin
  • Patent number: 9966448
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure with a source and a channel over the substrate; forming a spacer over the vertical structure; etching a portion of the spacer to expose the source; forming a first metal layer over the vertical structure; and thermal annealing the first metal layer to form a bottom silicide penetrating the source; and substantially removing the spacer.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
  • Patent number: 9954069
    Abstract: A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the barrier layer. As such, the source/drain region can be protected by the barrier layer from oxidation during manufacturing of the semiconductor device, e.g., the formation of the interlayer dielectric.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
  • Patent number: 9911661
    Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin