Patents by Inventor Huan-Just Lin

Huan-Just Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160293721
    Abstract: An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 6, 2016
    Inventors: Harry-Hak-Lay Chuang, Huan-Just Lin
  • Patent number: 9449880
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, Chih-Ming Lai, Huan-Just Lin, Ru-Gun Liu, Tsai-Sheng Gau, Wei-Liang Lin
  • Publication number: 20160254191
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, Chih-Ming Lai, Huan-Just Lin, Ru-Gun Liu, Tsai-Sheng Gau, Wei-Liang Lin
  • Publication number: 20160247896
    Abstract: A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventors: CHING-FENG FU, YU-CHAN YEN, CHIH-HSIN KO, CHUN-HUNG LEE, HUAN-JUST LIN, HUI-CHENG CHANG
  • Patent number: 9412614
    Abstract: A device comprises a first group of nanowires having a first pattern, a second group of nanowires having a second pattern, a third group of nanowires having a third pattern and a fourth group of nanowires having a fourth pattern, wherein the first pattern, the second pattern, the third pattern and the fourth pattern form a repeating pattern.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20160211370
    Abstract: A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the barrier layer. As such, the source/drain region can be protected by the barrier layer from oxidation during manufacturing of the semiconductor device, e.g., the formation of the interlayer dielectric.
    Type: Application
    Filed: March 30, 2016
    Publication date: July 21, 2016
    Inventors: CHIH-TANG PENG, TAI-CHUN HUANG, TENG-CHUN TSAI, CHENG-TUNG LIN, DE-FANG CHEN, LI-TING WANG, CHIEN-HSUN WANG, HUAN-JUST LIN, YUNG-CHENG LU, TZE-LIANG LEE
  • Publication number: 20160196979
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 7, 2016
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Patent number: 9368603
    Abstract: An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Huan-Just Lin
  • Patent number: 9343412
    Abstract: A method of forming a MOSFET structure is provided. In the method, an epitaxial layer is formed. A cap layer is formed above the epitaxial layer. A first trench is formed above the epitaxial layer. A protection layer is deposited within the first trench. The protection layer is a material selected from the group consisting of germanium and silicon-germanium.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Publication number: 20160111523
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: DE-FANG CHEN, Teng-chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Publication number: 20160111297
    Abstract: A method for self-aligned patterning includes providing a substrate, forming a patterned mandrel layer that includes a plurality of mandrel features, the patterned mandrel layer being formed on the substrate, depositing a first spacer layer over the mandrel layer, the first spacer layer comprising a first type of material, anisotropically etching the first spacer layer to leave a first set of spacers on sidewalls of the mandrel features, removing the mandrel layer, depositing a second spacer layer over remaining portions of the first set of spacers, and anisotropically etching the second spacer layer to form a second set of spacers on sidewalls of the first set of spacers.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Inventors: DE-FANG CHEN, HUAN-JUST LIN, CHUN-HUNG LEE, CHAO-CHENG CHEN
  • Patent number: 9318447
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
  • Publication number: 20160043173
    Abstract: A semiconductor structure, a semiconductor device, and a method for forming the semiconductor device are provided. In various embodiments, the method for forming the semiconductor device includes forming transistors on a substrate. Forming each transistor includes forming a doped region on the substrate. A nanowire is formed protruding from the doped region. An interlayer dielectric layer is deposited over the doped region. A dielectric layer is deposited over the interlayer dielectric layer and surrounding each of the nanowires. A first gate layer is deposited over the dielectric layer. The dielectric layer and first gate layer are etched to expose portions of the nanowires and the interlayer dielectric layer. A second gate layer is formed over the exposed interlayer dielectric layer and surrounding the first gate layer. Then, the second gate layer was patterned to remove the second gate layer on the interlayer dielectric layer between the transistors.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 11, 2016
    Inventors: Yung-Sung YEN, Huan-Just LIN, Chun-Hsiung LIN, Chi-Cheng HUNG
  • Patent number: 9252224
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Publication number: 20160027917
    Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.
    Type: Application
    Filed: October 7, 2015
    Publication date: January 28, 2016
    Inventors: CHENG-TUNG LIN, TENG-CHUN TSAI, LI-TING WANG, DE-FANG CHEN, BING-HUNG CHEN, HUANG-YI HUANG, HUI-CHENG CHANG, HUAN-JUST LIN, MING-HSING TSAI
  • Publication number: 20160020180
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 21, 2016
    Inventors: CHIH-TANG PENG, TAI-CHUN HUANG, TENG-CHUN TSAI, CHENG-TUNG LIN, DE-FANG CHEN, LI-TING WANG, CHIEN-HSUN WANG, HUAN-JUST LIN, YUNG-CHENG LU, TZE-LIANG LEE
  • Patent number: 9224833
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes the following operations: providing a vertical structure over a substrate; forming a first dielectric layer over the vertical structure and the substrate; laterally etching a sidewall of the first dielectric layer; replacing a portion of the first dielectric layer over the vertical structure with a second dielectric layer; and etching a portion of the first dielectric layer to expose the lateral surface of the vertical structure.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Publication number: 20150364358
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: TENG-CHUN TSAI, LI-TING WANG, DE-FANG CHEN, CHENG-TUNG LIN, CHIH-TANG PENG, CHIEN-HSUN WANG, BING-HUNG CHEN, HUAN-JUST LIN, YUNG-CHENG LU
  • Publication number: 20150348848
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20150348796
    Abstract: A device comprises a first group of nanowires having a first pattern, a second group of nanowires having a second pattern, a third group of nanowires having a third pattern and a fourth group of nanowires having a fourth pattern, wherein the first pattern, the second pattern, the third pattern and the fourth pattern form a repeating pattern.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 3, 2015
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin