Patents by Inventor Huan-Just Lin

Huan-Just Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF FORMING ISOLATION LAYER
    Publication number: 20200335388
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Teng-Chun TSAI, Bing-Hung CHEN, Chien-Hsun WANG, Cheng-Tung LIN, Chih-Tang PENG, De-Fang CHEN, Huan-Just LIN, Li-Ting WANG, Yung-Cheng LU
  • Tuning Threshold Voltage Through Meta Stable Plasma Treatment
    Publication number: 20200294805
    Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.
    Type: Application
    Filed: January 13, 2020
    Publication date: September 17, 2020
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan, Huan-Just Lin
  • Method of forming isolation layer
    Patent number: 10707114
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Bing-Hung Chen, Chien-Hsun Wang, Cheng-Tung Lin, Chih-Tang Peng, De-Fang Chen, Huan-Just Lin, Li-Ting Wang, Yung-Cheng Lu
  • Methods for controlling an end-to-end distance in semiconductor device
    Patent number: 10692720
    Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Huan-Just Lin, Huang-Ming Chen, Yang-Cheng Wu, Cheng-Hua Yang
  • Selective NFET/PFET Recess of Source/Drain Regions
    Publication number: 20200185278
    Abstract: A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 11, 2020
    Inventors: Yun-Min Chang, Chien-An Chen, Guan-Ren Wang, Peng Wang, Huang-Ming Chen, Huan-Just Lin
  • METHOD OF FORMING A VERTICAL DEVICE
    Publication number: 20200111887
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Inventors: DE-FANG CHEN, TENG-CHUN TSAI, CHENG-TUNG LIN, LI-TING WANG, CHUN-HUNG LEE, MING-CHING CHANG, HUAN-JUST LIN
  • Layer for Side Wall Passivation
    Publication number: 20200105586
    Abstract: A method of manufacturing a semiconductor device includes etching a via through a dielectric layer and an etch stop layer (ESL) to a source/drain contact, forming a recess in the top surface of the source/drain contact such that the top surface of the source/drain contact is concave, and forming an oxide liner on the sidewalls of the via. The oxide liner traps impurities left behind by the etching of the via through the dielectric layer and the ESL, wherein the etching, the forming the recess, and the forming the oxide liner are performed in a first chamber. The method further includes performing a pre-cleaning that removes the oxide layer and depositing a metal in the via.
    Type: Application
    Filed: September 12, 2019
    Publication date: April 2, 2020
    Inventors: Yun-Chang Hsu, Sheng-Liang Pan, Huan-Just Lin, Jack Kuo-Ping Kuo
  • Methods for Controlling an End-to-End Distance in Semiconductor Device
    Publication number: 20200083046
    Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 12, 2020
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Huan-Just Lin, Huang-Ming Chen, Yang-Cheng Wu, Cheng-Hua Yang
  • Self-Aligned Nanowire Formation Using Double Patterning
    Publication number: 20200083110
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Method of Forming MOSFET Structure
    Publication number: 20200058765
    Abstract: Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 20, 2020
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Selective NFET/PFET recess of source/drain regions
    Patent number: 10553492
    Abstract: A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Min Chang, Chien-An Chen, Guan-Ren Wang, Peng Wang, Huang-Ming Chen, Huan-Just Lin
  • Tuning threshold voltage through meta stable plasma treatment
    Patent number: 10535524
    Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan, Huan-Just Lin
  • Semiconductor methods and devices
    Patent number: 10515818
    Abstract: To pattern a gate electrode, a mandrel of material is initially deposited and then patterned. In an embodiment the patterning is performed by performing a first etching process and to obtain a rough target and then to perform a second etching process with different etch parameters to obtain a precise target. The mandrel is then used to form spacers which can then be used to form masks to pattern the gate electrode.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Kang Liu, Jr-Jung Lin, Huan-Just Lin, Ming-Hsi Yeh, Sung-Hsun Wu
  • Self-aligned nanowire formation using double patterning
    Patent number: 10504792
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Methods for controlling an end-to-end distance in semiconductor device
    Patent number: 10504729
    Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Huan-Just Lin, Huang-Ming Chen, Yang-Cheng Wu, Cheng-Hua Yang
  • Vertical device having a protrusion source
    Patent number: 10505014
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Self-Aligned Insulated Film for High-K Metal Gate Device
    Publication number: 20190341263
    Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • SELECTIVE NFET/PFET RECESS OF SOURCE/DRAIN REGIONS
    Publication number: 20190333820
    Abstract: A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Yun-Min Chang, Chien-An Chen, Guan-Ren Wang, Peng Wang, Huang-Ming Chen, Huan-Just Lin
  • Method of forming MOSFET structure
    Patent number: 10461170
    Abstract: A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Method of forming isolation layer
    Patent number: 10418271
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Cheng-Tung Lin, Chih-Tang Peng, Chien-Hsun Wang, Bing-Hung Chen, Huan-Just Lin, Yung-Cheng Lu