Patents by Inventor Hugh Mair

Hugh Mair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8964880
    Abstract: In an embodiment of the invention, a frequency divider in a phase-locked loop (PLL) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first direct current (DC) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Vishnu Ravinuthula, Dushmantha Rajapaksha, Hugh Mair
  • Patent number: 8812885
    Abstract: A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: August 19, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Philippe Royannez, Gilles Dubost, Christophe Vatinel, William Douglas Wilson, Vinod Menezes, Hugh Mair, James Sangwon Song
  • Publication number: 20140016718
    Abstract: In an embodiment of the invention, a frequency divider in a PLL (phase-locked loop) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first DC (direct current) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 16, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Vishnu Ravinuthula, Dushmantha Rajapaksha, Hugh Mair
  • Patent number: 8437214
    Abstract: A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: May 7, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Donald Mikan, Hugh Mair, Theodore W. Houston, Michael Patrick Clinton
  • Publication number: 20130003471
    Abstract: A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 3, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Donald George Mikan, JR., Hugh Mair, Theodore W. Houston, Michael Patrick Clinton
  • Patent number: 8248867
    Abstract: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: August 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Donald George Mikan, Jr., Hugh Mair, Theodore W. Houston, Michael Patrick Clinton
  • Patent number: 8051313
    Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: November 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Bixia Li, Hugh Mair, Minh Chau, Alice Wang, Uming Ko
  • Publication number: 20110069565
    Abstract: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line.
    Type: Application
    Filed: December 1, 2010
    Publication date: March 24, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Donald George Mikan, JR., Hugh Mair, Theodore W. Houston, Michael Patrick Clinton
  • Patent number: 7864600
    Abstract: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: January 4, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Donald George Mikan, Jr., Hugh Mair, Theodore W. Houston, Michael Patrick Clinton
  • Patent number: 7660150
    Abstract: A method is provided for writing to a memory cell having a read access circuit that is separate and isolatable from a write access circuit. The method comprises providing a logic state to be written to the memory cell onto a write bit line coupled to the memory cell through the write access circuit, changing a write word line that controls the write access circuit from a deactivated low voltage state to an activated high voltage state, and changing a read word line that controls the read access circuit from an activated low voltage state to a deactivated high voltage state, wherein the change in voltage on the read word line provides a voltage boost to the voltage on the write word line caused by the electrical coupling between the read word line and the write word line to provide write assist to the memory cell during a write operation.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: February 9, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Donald George Mikan, Jr., Hugh Mair
  • Publication number: 20090316500
    Abstract: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Inventors: Donald George Mikan, JR., Hugh Mair, Theodore W. Houston, Michael Patrick Clinton
  • Patent number: 7633314
    Abstract: System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: December 15, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Hugh Mair, Rolf Lagerquist
  • Publication number: 20090267638
    Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.
    Type: Application
    Filed: April 28, 2008
    Publication date: October 29, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Bixia Li, Hugh Mair, Minh Chau, Alice Wang, Uming Ko
  • Publication number: 20090168496
    Abstract: A method is provided for writing to a memory cell having a read access circuit that is separate and isolatable from a write access circuit. The method comprises providing a logic state to be written to the memory cell onto a write bit line coupled to the memory cell through the write access circuit, changing a write word line that controls the write access circuit from a deactivated low voltage state to an activated high voltage state, and changing a read word line that controls the read access circuit from an activated low voltage state to a deactivated high voltage state, wherein the change in voltage on the read word line provides a voltage boost to the voltage on the write word line caused by the electrical coupling between the read word line and the write word line to provide write assist to the memory cell during a write operation.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Donald George Mikan, JR., Hugh Mair
  • Publication number: 20080307240
    Abstract: An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Franck Dahan, Gilles Dubost, Gordon Gammie, Uming Ko, Hugh Mair, Sang-Won Song, Alice Wang, William D. Wilson
  • Publication number: 20080162969
    Abstract: A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
    Type: Application
    Filed: April 2, 2007
    Publication date: July 3, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Philippe Royannez, Gilles Dubost, Christophe Vantinel, William Douglas Wilson, Vinod Menezes, Hugh Mair, James Sangwon Song
  • Patent number: 7327185
    Abstract: An electronic system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply. The system further comprises a first circuit for providing a first value indicating a first potential capability of operational speed of at least one path in the plurality of circuit paths and a second circuit for providing a second value for indicating a second potential capability of operational speed of the at least one path in the plurality of circuit paths. The system further comprises circuitry for adjusting the system voltage, as provided by the voltage supply, in response to a relation between the first value and the second value.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: February 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Hugh Mair, Sumanth Gururajarao
  • Publication number: 20070120578
    Abstract: System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.
    Type: Application
    Filed: November 29, 2006
    Publication date: May 31, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hugh Mair, David Scott, Rolf Lagerquist
  • Publication number: 20070103202
    Abstract: System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 10, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hugh Mair, Rolf Lagerquist
  • Patent number: 7202729
    Abstract: Methods and apparatus to bias a backgate of a power switch while preventing latchup are disclosed. A disclosed method of biasing a backgate of a power switch comprises: if a voltage of a first power supply rises before a voltage of a second power supply, initially biasing the backgate with a voltage based on the first power supply; and if the voltage of the first power supply rises after the voltage of the second power supply, biasing the backgate with a voltage based on the second power supply.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: April 10, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Shanthi Bhagavatheeswaran, Srinivasan Venkatraman, Hugh Mair