Abstract: A temperature sensor arrangement (10), including a bandgap voltage generator (12), which is configured to provide an output voltage (Vbg); at least one semiconductor junction (14) for temperature sensing, which is biased by a biasing current flowing through said semiconductor junction (14); and at least one poly-resistor (Rb3) which is connected between the output (23) of the bandgap voltage generator (12) and the semiconductor junction (14), thereby providing said biasing current from the bandgap voltage generator (12) to the semiconductor junction (14).

Abstract: An electronic measuring device for measuring a physical parameter includes a differential analogue sensor formed from two capacitances—an excitation circuit of the differential analogue sensor providing to the sensor two electrical excitation signals which are inverted—a measuring circuit which generates an analogue electrical voltage which is a function determined from the value of the sensor, and a circuit for compensating for a possible offset of the sensor, which is formed from a compensation capacitance, which is excited by its own electrical excitation signal. The excitation circuit is arranged in order to be able to provide to an additional capacitance of the compensation circuit its own electrical excitation signal having a linear dependence on the absolute temperature with a determined proportionality factor in order to compensate for a drift in temperature of an electrical assembly of the measuring device comprising at least the compensation capacitance.

Abstract: A temperature sensor arrangement (10), including a bandgap voltage generator (12), which is configured to provide an output voltage (Vbg); at least one semiconductor junction (14) for temperature sensing, which is biased by a biasing current flowing through said semiconductor junction (14); and at least one poly-resistor (Rb3) which is connected between the output (23) of the bandgap voltage generator (12) and the semiconductor junction (14), thereby providing said biasing current from the bandgap voltage generator (12) to the semiconductor junction (14).

Abstract: An electronic measuring device for measuring a physical parameter includes a differential analogue sensor formed from two capacitances—an excitation circuit of the differential analogue sensor providing to the sensor two electrical excitation signals which are inverted—a measuring circuit which generates an analogue electrical voltage which is a function determined from the value of the sensor, and a circuit for compensating for a possible offset of the sensor, which is formed from a compensation capacitance, which is excited by its own electrical excitation signal. The excitation circuit is arranged in order to be able to provide to an additional capacitance of the compensation circuit its own electrical excitation signal having a linear dependence on the absolute temperature with a determined proportionality factor in order to compensate for a drift in temperature of an electrical assembly of the measuring device comprising at least the compensation capacitance.

Abstract: A communication beacon including a calculation unit associated with a memory module for data storage and with a communication circuit, the beacon being powered by a power unit, the communication circuit including a first interface unit using a first protocol, a second interface unit using a second protocol, the memory unit including a first memory unit and a second memory unit each memory unit being electrically connected to each interface unit.

Abstract: A communication beacon including a calculation unit associated with a memory module for data storage and with a communication circuit, the beacon being powered by a power unit, the communication circuit including a first interface unit using a first protocol, a second interface unit using a second protocol, the memory unit including a first memory unit and a second memory unit each memory unit being electrically connected to each interface unit.

Abstract: The secure integrated circuit (1) further includes storage means (2) in which confidential data is stored, such as an encryption programme and at least an encryption key, and a microprocessor unit (3) for executing the encryption programme. Said circuit further includes an oscillator stage (4, 5) supplying clock signals (CLK) in particular for clocking the sequence of operations in the microprocessor unit (3), and a random number generator (6) connected to the microprocessor unit. A random number (RNGosc) generated by the random number generator is supplied to the input of the oscillator stage to configure it such that the frequency of the clock signals supplied by the oscillator stage depends on said random number. The oscillator stage includes an RC type oscillator, in which a certain number of resistors and/or capacitors can be selected by the random number introduced at the input of the oscillator stage.

Abstract: The present invention concerns a data updating method for a non-volatile memory broken down into a plurality of similar memory subdivisions that can be erased independently of each other and among which at least two memory subdivisions (SRA, SRB) are reserved for updating data contained in each of said subdivisions (SM). The method implemented enables the execution time of an update to be reduced by simultaneously erasing the non-reserved memory subdivision (SM) to be updated and an unused reserved memory subdivision (SRB).

Abstract: This method uses a tester (T) capable of being connected to an integrated circuit (CI) to be tested. A random number (RNG-C) is generated and ciphered using a key (k) by a cipher algorithm to obtain a password (Gk(RNG)-C). The random number (RNG-C) is sent to the tester (T) in which the received random number (RNG-C) is ciphered using the same key (k) by a same cipher algorithm to generate therein a second password (Gk(RNG)-T). This latter is sent to the integrated circuit (CI) to be compared to the first password (Gk(RNG)-C). The test of the confidential parts (1) of the circuit is only authorised if the two passwords exhibit the required match.

Abstract: The secure integrated circuit (1) further includes storage means (2) in which confidential data is stored, such as an encryption programme and at least an encryption key, and a microprocessor unit (3) for executing the encryption programme. Said circuit further includes an oscillator stage (4, 5) supplying clock signals (CLK) in particular for clocking the sequence of operations in the microprocessor unit (3), and a random number generator (6) connected to the microprocessor unit. A random number (RNGosc) generated by the random number generator is supplied to the input of the oscillator stage to configure it such that the frequency of the clock signals supplied by the oscillator stage depends on said random number. The oscillator stage includes an RC type oscillator, in which a certain number of resistors and/or capacitors can be selected by the random number introduced at the input of the oscillator stage.

Abstract: The present invention concerns a data updating method for a non-volatile memory broken down into a plurality of similar memory subdivisions that can be erased independently of each other and among which at least two memory subdivisions (SRA, SRB) are reserved for updating data contained in each of said subdivisions (SM). The method implemented enables the execution time of an update to be reduced by simultaneously erasing the non-reserved memory subdivision (SM) to be updated and an unused reserved memory subdivision (SRB).

Abstract: This method uses a tester (T) capable of being connected to an integrated circuit (CI) to be tested.